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Table 11-25. PITC Field Descriptions (Continued)
Bits
Name
16Ð31 Ñ
Reserved, should be cleared.
11.11.3 PIT Register (PITR)
The PIT register (PITR) is a read-only register that shows the current value in the periodic
interrupt down counter. Writes to PITR do not affect it; reads do not affect the counter.
Bit
0
1
Field
Reset
R/W
Addr
Bit
16
17
Field
Reset
R/W
Addr
Table 11-26 describes PITR Þelds.
Bits
Name
0Ð15
PIT
Periodic interrupt timing count. Holds the current count remaining for the periodic timer. Writes do not
affect PIT.
16Ð31 Ñ
Reserved, should be cleared.
11.12 General SIU Timers Operation
The following sections provide detailed information on the operation of the SIU timers.
11.12.1 Freeze Operation
The FRZ signal is asserted as a result of entry into debug mode, or as a result of actions
performed by a software monitor debugger. When the FRZ signal is asserted, the clocks to
the software watchdog, PIT, real-time clock, timebase counter, and decrementer can be
disabled. This is controlled by the associated bits in the control register of each timer. If they
are programmed to stop counting when FRZ is asserted, the counters maintain their values
until FRZ is negated. The bus monitor, however, will be enabled regardless of this signalÕs
state.
MOTOROLA
2
3
4
5
(IMMR & 0xFFFF0000) + 0x248
18
19
20
21
22
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x24A
Figure 11-31. PIT Register (PITR)
Table 11-26. PITR Field Descriptions
Chapter 11. System Interface Unit
Description
6
7
8
9
10
PIT
Ñ
R
23
24
25
26
Ñ
R
Description
Part III. Configuration
11
12
13
14
15
27
28
29
30
31
11-33
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