Motorola MPC860 PowerQUICC User Manual page 319

Table 12-3. Hard Reset Configuration Word Field Descriptions (Continued)
Bits Name
11Ð1 DBPC Debug port pins conÞguration. Determines the active pins for the development port.
2 00 ALE_B/DSCK/AT1, IP_B6/DSDI/AT0, OP3/MODCK2/DSDO, and IP_B7/PTR/AT3 function as
deÞned by DBGC
TCK/DSCK functions as DSCK
TDI/DSDI functions as DSDI
TDO/DSDO functions as DSDO
01 ALE_B/DSCK/AT1, IP_B6/DSDI/AT0, OP3/MODCK2/DSDO, and IP_B7/PTR/AT3 function as
deÞned by DBGC
TCK/DSCK functions as TCK
TDI/DSDI functions as TDI
TDO/DSDO functions as TDO
10 Reserved
11 ALE_B/DSCK/AT1 functions as DSCK
IP_B6/DSDI/AT0 functions as DSDI
OP3/MODCK2/DSDO functions as DSDO
IP_B7/PTR/AT3 functions as PTR
TCK/DSCK functions as TCK
TDI/DSDI functions as TDI
TDO/DSDO functions as TDO
13Ð1 EBDF External bus division factor. DeÞnes the frequency division factor between GCLK1/GCLK2 and
4 GCLK1_50/GCLK2_50. CLKOUT is similar to GCLK2_50. GCLK2_50 and GCLK1_50 are used by the
system interface unit and memory controller to interface with the external system. Refer to Chapter 15,
ÒClocks and Power ControlÓ for additional information.
00 Full speed bus
01 Half speed bus
10 Reserved
11 Reserved
15 Ñ Reserved. This bit is reserved for future use and should be allowed to ßoat.
12.3.2 Soft Reset
When a soft reset event occurs, the MPC860 reconÞgures the development port. See
Section 37.3.1.2, ÒEntering Debug Mode,Ó and Section 37.3.2.3.3, ÒSelection of
Development Port Clock Mode.Ó
MOTOROLA
Description
Chapter 12. Reset
Part III. Configuration
12-11