Motorola MPC860 PowerQUICC User Manual page 778

Part V. The Communications Processor Module
¥ Another protocol can be performed on the other half of the SCC
¥ MC68360-compatible SYNC options
29.2 SCC Transparent Channel Frame Transmission
Process
The transparent transmitter is designed to work almost no intervention from the core. When
the core enables the SCC transmitter in transparent mode, it starts sending idles, which are
logic high or encoded ones, as programmed in GSMR_L[TEND]. The SCC polls the Þrst
BD in the TxBD table. When there is a message to send, the SCC fetches data from
memory, loads the transmit FIFO, and waits for transmitter synchronization, which is
achieved with CTS or by waiting for the receiver to achieve synchronization, depending on
GSMR_H[TXSY]. Transmission begins when transmitter synchronization is achieved.
When all BD data has been sent, if TxBD[L] is set, the SCC writes the message status bits
into the BD, clears TxBD[R], and sends idles until the next BD is ready. If it is ready, some
idles are still sent. The transmitter resumes sending only after it achieves synchronization.
If TxBD[L] is cleared when the end of the BD is reached, only TxBD[R] is cleared and the
transmitter moves immediately to the next buffer to begin transmission with no gap on the
serial line between buffers. Failure to provide the next buffer in time causes a transmit
underrun which sets SCCE[TXE].
In both cases, an interrupt is issued according to TxBD[I]. By appropriately setting
TxBD[I] in each BD, interrupts are generated after each buffer or group of buffers is sent.
The SCC then proceeds to the next BD in the table and any whole number of bytes can be
sent. If GSMR_H[REVD] is set, the bit order of each byte is reversed before being sent; the
msb of each octet is sent Þrst.
Setting GSMR_H[TFL] makes the transmit FIFO smaller and reduces transmitter latency,
but it can cause transmitter underruns at higher transmission speeds. An optional CRC,
selected in GSMR_H[TCRC], can be appended to each transparent frame if it is enabled in
the TxBD.
When the time-slot assigner (TSA) is used with a transparent-mode channel,
synchronization is provided by the TSA. There is a start-up delay for the transmitter, but
delays will always be some whole number of complete TSA frames. This means that n-byte
transmit buffers can be mapped directly into n-byte time slots in the TSA frames.
29.3 SCC Transparent Channel Frame Reception
Process
When the core enables the SCC receiver in transparent mode, it waits to achieve
synchronization before data is received. The receiver can be synchronized to the data by a
synchronization pulse or SYNC pattern.
29-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA