Motorola MPC860 PowerQUICC User Manual page 571

Table 20-3 describes the SDSR bit settings.
Bits Name
0 SBER SDMA channel bus error. Indicates an error caused the SDMA channel to terminate during a read or
write cycle. The SDMA bus error address can be retrieved from the SDMA address register (SDAR).
1Ð5 Ñ Reserved
6 DSP2 DSP chain2 (Tx) interrupt. See Section 36.10, ÒDSP Event/Mask Registers (SDSR/SDMR).Ó
7 DSP1 DSP chain1 (Rx) interrupt. See Section 36.10, ÒDSP Event/Mask Registers (SDSR/SDMR).Ó
20.2.3 SDMA Mask Register (SDMR)
The read/write SDMA mask register (SDMR) has the same bit format as SDSR; see above
Figure 20-4. If a bit in the SDMR is set, the corresponding interrupt in the SDSR is enabled;
if the bit is cleared, the corresponding interrupt is masked. Reset clears SDMR. Its internal
address (IMMR offset) is 0x90C.
20.2.4 SDMA Address Register (SDAR)
The 32-bit, read-only SDMA address register (SDAR) holds the current system address
being accessed and is used to diagnose an SDMA bus error. SDAR is undeÞned at reset. Its
internal address (IMMR offset) is 0x904.
20.3 IDMA Emulation
The CPM can be conÞgured to emulate two general-purpose independent DMA (IDMA)
channels using the two physical SDMA channels. In IDMA emulation mode, the user
speciÞes a memory/memory or peripheral/memory transfer as if using dedicated DMA
hardware.
IDMA uses two addressing modesÑdual-address and single-address. In IDMA
dual-address transfers, data is read into internal storage, packed onto the bus, and then
written to the destination. Dual-address transfers can take several bus cycles depending on
the peripheralÕs port size. In contrast, single-address (ßy-by) IDMA bypasses internal
storage, transferring data directly between memory and a peripheral in a single bus cycle.
See Section 20.3.8, ÒIDMA TransfersÑDual-Address and Single-Address.Ó
The IDMA controller supports two buffer handling modesÑauto-buffering, and
buffer-chaining. In buffer-chaining, an IDMA moves a connected series of BDs called a
chain without interruption. Auto-buffering allows a buffer chain to be repeatedly
transferred in a loop without user intervention. See Section 20.3.4.2, ÒAuto-Buffering and
Buffer-Chaining.Ó
Single-buffering is a special, low-latency IDMA transfer mode optimized for transferring
one buffer from a peripheral to memory. This low-overhead mode uses single-address
MOTOROLA
Table 20-3. SDSR Field Descriptions
Chapter 20. SDMA Channels and IDMA Emulation
Part V. The Communications Processor Module
Description
20-5