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Table 14-1. MPC860 Signal Overview (Continued)
Signal
Pins Active I/O
D[0Ð31]
32
High
Data Bus
DP[0Ð3]
4
High
Parity Bus
TA
1
Low
Transfer
Acknowledge
TEA
1
Low
Transfer Error
Acknowledge
BI
1
Low
Burst Inhibit
MOTOROLA
Data
The data bus has the following byte lane assignments:
Data Byte
Byte Lane
D[0Ð7]
0
D[8Ð15]
1
D[16Ð23]
2
D[24Ð31]
3
O
Driven by the MPC860 when it is external bus master and it initiated a write
transaction to a slave device. For single-beat transactions, the byte lanes not
selected for the transfer by the A[30Ð31] and TSIZ[0Ð1] will not supply valid data.
I
Driven by the slave in a read transaction. For single-beat transactions, the byte
lanes not selected for the transfer by the A[30Ð31] and TSIZ[0Ð1] will not be
sampled by the MPC860
Each parity line corresponds to each one of the data bus lanes:
Data Bus Byte
Parity Line
D[0Ð7]
DP0
D[8Ð15]
DP1
D[16Ð23]
DP2
D[24Ð31]
DP3
O
Driven by the MPC860 when it is external bus master and it initiated a write
transaction to a slave device. Each line has the parity value (even or odd) of its
corresponding data bus byte. For single-beat transfers, byte lanes not selected by
A[30Ð31] and TSIZ[0Ð1] will not have a valid parity line.
I
Driven by the slave in a read transaction. Each parity line is sampled by the
MPC860 and checked (if enabled) against the expected value parity value (even
or odd) of its corresponding data bus byte. For single-beat transfers, byte lanes
not selected by A[30Ð31] and TSIZ[0Ð1] are not sampled by the MPC860 and its
parity lines will not be checked.
Transfer Cycle Termination
I
Driven by the slave device to which the current transaction is addressed.
Indicates that the slave received the data on the write cycle or returned data on
the read cycle. If the transaction is a burst, TA should be asserted for each beat.
O
Driven by the MPC860 when the slave device is controlled by the on-chip memory
controller or PCMCIA interface.
I
Driven by the slave device to which the current transaction is addressed.
Indicates that an error condition occurred during the bus cycle.
O
Driven by the MPC860 when the internal bus monitor detects a bus error.
I
Driven by the slave device to which the current transaction was addressed.
Indicates that the current slave does not support burst mode.
O
Driven by the MPC860 when the on-chip memory controller controls the slave.
Chapter 14. MPC860 External Bus Interface
Part IV. Hardware Interface
Description
14-5
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