Motorola MPC860 PowerQUICC User Manual page 650

Part V. The Communications Processor Module
4. If the time-slot assigner (TSA) is used, the serial interface (SI) must be conÞgured.
If the SCC is used in NMSI mode, SICR must still be initialized.
5. Write all GSMR bits except ENT or ENR.
6. Write the PSMR.
7. Write the DSR.
8. Initialize the required values for this SCCÕs parameter RAM.
9. Clear out any current events in SCCE (optional).
10. Write ones to SCCM register to enable interrupts.
11. Write CICR to conÞgure the SCC interrupt priority.
12. Clear out any current interrupts in the CIPR (optional).
13. Write the CIMR to enable interrupts to the CPIC.
14. Set GSMR_L[ENT] and GSMR_L[ENR].
Descriptors can have their R or E bits set at any time. Notice that the CPCR does not need
to be accessed after a hard reset. An SCC should be disabled and reenabled after any
dynamic change to its parallel I/O ports or serial channel physical interface conÞguration.
A full reset can also be implemented using CPCR[RST].
22.3.4 Controlling SCC Timing with RTS, CTS, and CD
When GSMR_L[DIAG] is programmed to normal operation, CD and CTS are controlled
by the SCC. In the following subsections, it is assumed that GSMR_L[TCI] is zero,
implying normal transmit clock operation.
22.3.4.1 Synchronous Protocols
RTS is asserted when the SCC data is loaded into the Tx FIFO and a falling Tx clock occurs.
At this point, the SCC starts sending data once appropriate conditions occur on CTS. In all
cases, the Þrst data bit is the start of the opening ßag, sync pattern, or preamble.
Figure 22-9 shows that the delay between RTS and data is 0 bit times, regardless of
GSMR_H[CTSS]. This operation assumes that CTS is already asserted to the SCC or that
CTS is reprogrammed to be a parallel I/O line, in which case CTS to the SCC is always
asserted. RTS is negated one clock after the last bit in the frame.
22-18 MPC860 PowerQUICC UserÕs Manual MOTOROLA