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Set-associative. Aspect of cache organization in which the cache space is
SigniÞcand. The component of a binary ßoating-point number that consists
Slave. A device that responds to the masterÕs address. A slave receives data
Static branch prediction. Mechanism by which software (for example,
Sticky bit. A bit that when set must be cleared explicitly.
Superscalar machine. A machine that can issue multiple instructions
Supervisor mode. The privileged operation state of a processor. In
Synchronization. A process to ensure that operations occur strictly in order.
Synchronous exception. An exception that is generated by the execution of
System memory. The physical memory available to a processor.
T
Time-division multiplex (TDM). A single serial channel used by several
TLB (translation lookaside buffer) A cache that holds recently-used page
Throughput. The measure of the number of instructions that are processed
U
UISA (user instruction set architecture). The level of the architecture to
Glossary--10
divided into sections, called sets. The cache controller associates a
particular main memory address with the contents of a particular set,
or region, within the cache.
of an explicit or implicit leading bit to the left of its implied binary
point and a fraction Þeld to the right.
on a write cycle and gives data to the master on a read cycle.
compilers) can give a hint to the machine hardware about the
direction a branch is likely to take.
concurrently from a conventional linear instruction stream.
supervisor mode, software, typically the operating system, can
access all control registers and can access the supervisor memory
space, among other privileged operations.
See Context synchronization and Execution synchronization.
a particular instruction or instruction sequence. There are two types
of synchronous exceptions, precise and imprecise.
channels taking turns.
table entries.
per clock cycle.
which user-level software should conform. The UISA deÞnes the
MPC860 PowerQUICC UserÕs Manual
MOTOROLA
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