Motorola MPC860 PowerQUICC User Manual page 255

Table 9-19. MD_CAM Field Descriptions (Continued)
Bits Name
24Ð26 PS Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
27 SH Shared page
0 This entry matches only if the ASID Þeld in the DTLB entry matches the value in M_CASID
1 ASID comparison is disabled for the entry
28Ð31 ASID Address space ID of the DTLB entry to be compared with M_CASID[CASID]
9.8.12.5 DMMU RAM Entry Read Register 0 (MD_RAM0)
The DMMU RAM entry read register 0 (MD_RAM0), shown in Figure 9-21, contains the
physical page number and page attributes of an entry indexed by MD_CTR[DTLB_INDX].
This register is updated when any value is written to MD_CAM.
Bit 0 1 2
Field
Reset
R/W
Bit 16 17 18
Field RPN
Reset
R/W
SPR
Figure 9-21. DMMU RAM Entry Read Register 0 (MD_RAM0)
Table 9-20 describes MD_RAM0 Þelds.
Bits Name
0Ð19 RPN Real (physical) page number
20Ð22 PS Page size. (Values not shown are reserved)
000 4 Kbyte
001 16 Kbyte
011 512 Kbyte
111 8 Mbyte
23Ð26 APGI Access protection group inverted. Access protection group number in oneÕs complement format
27 G Guarded memory attribute for the entry
0 Nonguarded memory
1 Guarded memory
MOTOROLA
3 4 5 6
19 20 21 22
PS
Table 9-20. MD_RAM0 Field Descriptions
Chapter 9. Memory Management Unit (MMU)
Part II. PowerPC Microprocessor Module
Description
7 8 9 10
RPN
Ñ
R
23 24 25 26
APGI
Ñ
R/W
825
Description
11 12 13 14
27 28 29 30
G WT CI Ñ
9-29
15
31