Motorola MPC860 PowerQUICC User Manual page 180

Part II. PowerPC Microprocessor Module
Table 7-5. Register Settings after a Machine Check Interrupt Exception
Register
SRR0 Set to the EA of the instruction that caused the exception.
SRR1 1 1 for instruction fetch-related errors; 0 for load/store-related errors.
2Ð4 0
10Ð15 0
Others Loaded from MSR[16-31]. SRR1[30] is cleared only by loading a zero from MSR[RI].
MSR IP No change
ME 0
LE Copied from the ILE setting of the interrupted process
Others 0
DSISR Set when the load/store bus is used:
0Ð14 0
15Ð16 Set to bits 29-30 of the instruction if X-form instruction and to 0b00 if D-form.
17 Set to bit 25 of the instruction if X-form instruction and to bit 5 if D-form.
18Ð21 Set to bits 21-24 of the instruction if X-form instruction and to bits 1-4 if D-form.
22Ð31 Set to bits 6-15 of the instruction.
DAR When the load/store bus is used, DAR holds the EA of the data access that caused the exception.
7.1.2.3 DSI Exception (0x00300)
DSI exceptions are never generated by the hardware. Software may branch to this location
as a result of either implementation speciÞc DTLB error interrupt or implementation
speciÞc STLB miss interrupt.
7.1.2.4 ISI Exception (0x00400)
ISI exceptions is never generated by the hardware. The software may branch to this location
as a result of an implementation-speciÞc ITLB error interrupt.
7.1.2.5 External Interrupt Exception (0x00500)
In the MPC860 the external interrupt is generated by the on-chip interrupt controller. It is
software acknowledged and maskable by MSR[EE], which hardware clears automatically
to disable external interrupts when any exception is taken.
When an external interrupt is detected, program execution continues until all previous
instructions retire from the completion queue and the exception is assigned to the
instruction last entry in the completion queue (at point B in Table 7-19.) However, the
following conditions must be met before the instruction at the end of the queue can retire.
¥ The instruction must be completed without exception
¥ The instruction must either be a mtspr, mtmsr, rÞ, a memory reference, or a
memory- or cache-control instruction.
Instructions not Þtting these criteria are discarded along with any execution results. After
the exception handler completes, execution resumes with the Þrst instruction that was
discarded. If all the instructions in the completion queue were allowed to complete,
execution at the end of the exception handler resumes with the next instruction. External
7-6
Setting
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