Motorola MPC860 PowerQUICC User Manual page 163

6.2.4.2.3 Integer Store Instructions
For integer store instructions, the contents of rS are stored into the byte, half word, word,
or double word in memory addressed by the effective address (EA). Many store instructions
have an update form, in which rA is updated with the EA. For these forms, the following
rules apply:
¥ If rA ¹ 0, the EA is placed into rA.
¥ If rS = rA, the contents of rS are copied to the target memory element, then the
generated EA is placed into rA (rS).
The MPC860 defines store with update instructions with rA = 0 and integer store
instructions with the CR update option enabled (Rc[31] = 1) to be invalid forms. Table 6-8
lists integer store instructions for the MPC860.
Store Byte
Store Byte Indexed
Store Byte with Update
Store Byte with Update Indexed
Store Half Word
Store Half Word Indexed
Store Half Word with Update
Store Half Word with Update Indexed
Store Word
Store Word Indexed
Store Word with Update
Store Word with Update Indexed
6.2.4.2.4 Integer Load and Store with Byte-Reverse Instructions
Table 6-9 describes integer load and store with byte-reverse instructions. When used in a
PowerPC system operating with the default big-endian byte order, these instructions have
the effect of loading and storing data in little-endian order. Likewise, when used in a
PowerPC system operating with little-endian byte order, these instructions have the effect
of loading and storing data in big-endian order. For more information about big-endian and
little-endian byte ordering, see ÒByte OrderingÓ in Chapter 3, ÒOperand Conventions,Ó in
The Programming Environments Manual.
MOTOROLA
Table 6-8. Integer Store Instructions
Name
Chapter 6. MPC860 Instruction Set
Part II. PowerPC Microprocessor Module
Mnemonic
stb rS,d(rA)
stbx rS,rA,rB
stbu rS,d(rA)
stbux rS,rA,rB
sth rS,d(rA)
sthx rS,rA,rB
sthu rS,d(rA)
sthux rS,rA,rB
stw rS,d(rA)
stwx rS,rA,rB
stwu rS,d(rA)
stwux rS,rA,rB
Syntax
6-13