Motorola MPC860 PowerQUICC User Manual page 162

Part II. PowerPC Microprocessor Module
Section 6.2.2.2, ÒEffective Address Calculation,Ó for information about calculating
effective addresses. Note that the MPC860 is optimized for load and store operations that
are aligned on natural boundaries, and operations that are not naturally aligned may suffer
performance degradation. Refer to Section 7.1.2.6.1, ÒInteger Alignment Exceptions,Ó for
additional information about load and store address alignment exceptions.
6.2.4.2.2 Register Indirect Integer Load Instructions
For integer load instructions, the byte, half word, or word addressed by the EA is loaded
into rD. Many integer load instructions have an update form, in which rA is updated with
the generated effective address. For these forms, the EA is placed into rA and the memory
element (byte, half word, word, or double word) addressed by EA is loaded into rD.
Table 6-7 lists the integer load instructions.
Load Byte and Zero
Load Byte and Zero Indexed
Load Byte and Zero with Update
Load Byte and Zero with Update Indexed
Load Half Word and Zero
Load Half Word and Zero Indexed
Load Half Word and Zero with Update
Load Half Word and Zero with Update Indexed
Load Half Word Algebraic
Load Half Word Algebraic Indexed
Load Half Word Algebraic with Update
Load Half Word Algebraic with Update Indexed
Load Word and Zero
Load Word and Zero Indexed
Load Word and Zero with Update
Load Word and Zero with Update Indexed
6-12
Table 6-7. Integer Load Instructions
Name
MPC860 PowerQUICC UserÕs Manual
Mnemonic
lbz rD,d(rA)
lbzx rD,rA,rB
lbzu rD,d(rA)
lbzux rD,rA,rB
lhz rD,d(rA)
lhzx rD,rA,rB
lhzu rD,d(rA)
lhzux rD,rA,rB
lha rD,d(rA)
lhax rD,rA,rB
lhau rD,d(rA)
lhaux rD,rA,rB
lwz rD,d(rA)
lwzx rD,rA,rB
lwzu rD,d(rA)
lwzux rD,rA,rB
Syntax
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