Motorola MPC860 PowerQUICC User Manual page 414

Table of Contents

Advertisement

Part IV. Hardware Interface
A state diagram describing transitions between the various low-power modes is shown in
Figure 15-13.
1
Software-Initiated
1
Software-Initiated
CPM_ACT
1
Software-Initiated
or CPM_ACT * (CSRC=1)
1
Software-Initiated
1
Software-Initiated
1
Software-Initiated
Software-init
Power Failure
Legend:
CPM_ACT = (CPM Activity) * (SCCR[CRQEN] = 1)
MSRPOW = (MSR[POW] = 0) * (SCCR[PRQEN] = 1)
1
Software is active only in normal high/low modes.
2
Software initiation of power-down mode requires that the TEXP output be used by external logic to gate main power (VDDH, VDDL,
and VDDSYN).
Figure 15-13.
15-20
(CPM_ACT + MSRPOW + Interrupt) + CSRC
Normal Low
CPM_ACT * MSRPOW * Interrupt Cleared * CSRC
LPM=00, CSRC=1
Doze Low
LPM=01, CSRC=1
CPM_ACT * CSRC
Doze High
LPM=01, CSRC=0
Sleep Mode
LPM=10
Deep-Sleep Mode
LPM=11
TEXPS=1
Power-Down Mode
2
: LPM=11 and TEXPS=0
or Power Fail
MPC860
MPC860 PowerQUICC UserÕs Manual
CPM Interrupt * SCCR[PRQEN]
Wake-Up: 3-4 GCLKx
Clocks
IRQx + RTC/PIT/TB/DEC
Interrupt
Wake-Up: 3-4 VCOOUT
Clocks
IRQx + RTC/PIT/TB/DEC
Interrupt
Wake-Up: 500 OSCCLK
Clocks
(RTC/PIT/TB/DEC Interrupt
Followed
by HRESET)
or
(HRESET Only)
Software-Initiated
HRESET
Low-Power Mode Flowchart
Normal
High Mode
LPM=00,
[CSRC=0
or
(CSRC=1) * Interrupt]
1
MOTOROLA

Advertisement

Table of Contents
loading

Table of Contents