Motorola MPC860 PowerQUICC User Manual page 249

Table 9-12. MD_RPN Field Descriptions (Continued)
4-Kbyte Pages AND
Bits Name
(MD_CTR[PPM] = 1)
29 SH Shared page
0 This entry matches only if the ASID Þeld in the DTLB entry matches the M_CASID value.
1 ASID comparison is disabled for the entry.
30 CI Cache-inhibit attribute for the entry.
31 V Entry valid indication.
9.8.8 MMU Tablewalk Base Register (M_TWB)
The MMU tablewalk base register (M_TWB), shown in Figure 9-13, contains a pointer to
the level-one table to be used in hardware-assisted tablewalk mode.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field
Reset
R/W
SPR
Figure 9-13. MMU Tablewalk Base Register (M_TWB)
Table 9-13 describes MWB Þelds.
Bits Name
0Ð19 L1TB Tablewalk level-one base value
20Ð29 L1INDX Level-one table index. Ignored on write. Returns MD_EPN[0Ð9] on read when MD_CTR[TWAM] =
1. Returns MD_EPN[2Ð11] on read when MD_CTR[TWAM] = 0
30Ð31 Ñ Reserved. Ignored on write. Returns 0 on read.
9.8.9 MMU Current Address Space ID Register (M_CASID)
The MMU current address space ID register (M_CASID), shown in Figure 9-14, is used to
compare the current EA with the ASID Þeld in the TLB entry when searching for a match.
Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Field
Reset
R/W
SPR
Figure 9-14. MMU Current Address Space ID Register (M_CASID)
MOTOROLA
Greater than 4-Kbyte Pages OR MD_CTR[PPM] = 0
L1TB
Ñ
Table 9-13. M_TWB Field Descriptions
Ñ
Chapter 9. Memory Management Unit (MMU)
Part II. PowerPC Microprocessor Module
L1TB
R/W
796
Description
Ñ
R/W
793
L1INDX Ñ
00
CASID
9-23