Motorola MPC860 PowerQUICC User Manual page 843

31.8 SPI Master Programming Example
The following sequence initializes the SPI to run at a high speed in master mode:
1. ConÞgure port B to enable SPIMISO, SPIMOSI, and SPICLK. Set PBPAR[28, 29,
30] and PBDIR[28, 29, 30], then clear PBODR[28, 29, 30].
For multimaster operation, connect the internal SPISEL input to the SPI by setting
PBPAR[31] and PBDIR[31] and by clearing PBODR[31].
2. ConÞgure a parallel I/O signal to operate as the SPI select output signal if needed.
If PB15 is chosen, clear PBODR[15] and PBPAR[15] and set PBDIR[15]. Then
clear PBDAT[15] to constantly assert the select signal.
3. Write RBASE and TBASE in the SPI parameter RAM to point to the RxBD and
TxBD tables in the dual-port RAM. Assuming one RxBD followed by one TxBD at
the beginning of the dual-port RAM, write RBASE with 0x0000 and TBASE with
0x0008.
4. Execute the
INIT RX AND TX PARAMETERS
5. Write 0x0001 to the SDCR to initialize the SDMA conÞguration register (SDCR).
6. Write RFCR and TFCR with 0x10 for normal operation.
7. Write MRBLR with the maximum number of bytes per Rx buffer. For this case,
assume 16 bytes, so MRBLR = 0x0010.
8. Initialize the RxBD. Assume the Rx buffer is at 0x0000_1000 in main memory.
Write 0xB000 to RxBD[Status and Control], 0x0000 to RxBD[Data Length]
(optional), and 0x0000_1000 to RxBD[Buffer Pointer].
9. Initialize the TxBD. Assume the Tx buffer is at 0x0000_2000 in main memory and
contains Þve 8-bit characters. Write 0xB800 to TxBD[Status and Control], 0x0005
to TxBD[Data Length], and 0x0000_2000 to TxBD[Buffer Pointer].
10. Write 0xFF to SPIE to clear any previous events.
11. Write 0x37 to SPIM to enable all possible SPI interrupts.
12. Write 0x0000_0020 to the CPM interrupt mask register (CIMR). This sets
CIMR[SPI] to enable SPI-generated system interrupts. The CICR should also be
initialized.
13. Write 0x0370 to SPMODE to enable normal operation (not loopback), master mode,
SPI enabled, 8-bit characters, and the fastest speed possible.
14. Clear PBDAT[D15], assuming PB15 is chosen, to assert the SPI select output signal.
15. Set SPCOM[STR] to start the transfer.
After 5 bytes are sent, the TxBD is closed because TxBD[L] is set. The RxBD is closed
when the TxBD closes.
MOTOROLA
Part V. The Communications Processor Module
Chapter 31. Serial Peripheral Interface
command by writing 0x0051 to CPCR.
31-17