Motorola MPC860 PowerQUICC User Manual page 574

Part V. The Communications Processor Module
Table 20-5 describes DCMR Þelds.
Bits Name
0Ð10 Ñ Reserved. Should be cleared.
11Ð12 SIZE Peripheral port size. Determines the operand transfer size per DREQx assertion for
peripheral/memory transfers, but not for memory/memory transfers. (For memory/memory
transfers the size is determined only by address alignment and the amount of data remaining to be
transferred.)
00 Word length.
01 Half-word length.
10 Byte length.
11 Reserved.
Note that the memory port size is transparent to the IDMA. The SIU emulates a 32-bit port size
regardless of the actual memory port size.
13Ð14 S/D Source/destination. DeÞnes the source and destinationÑmemory or peripheral. For memory
accesses, the CP automatically increments the address.
00 Read from memory; write to memory.
01 Read from peripheral; write to memory.
10 Read from memory; write to peripheral.
11 Reserved.
15 SC Single-cycle. Selects single- or dual-cycle mode.
0 Dual-cycle (dual-address) mode.
1 Single-cycle (single-address) mode.
20.3.3.2 IDMA Status Registers (IDSR1 and IDSR2)
The IDMA status registers (IDSR1 and IDSR2) report transfer events. When the IDMA
controller recognizes an event, it sets the corresponding event bit in the IDSR. IDSR bits
are cleared by writing ones; writing zeros has no effect. Figure 20-6 shows the register
format.
Bit 0
Field
Reset
R/W
Addr
Figure 20-6. IDMA Status Registers (IDSR1/IDSR2)
Table 20-6 describes the IDSR Þelds.
Bits Name
0Ð4 Ñ Reserved
5 AD Auxiliary done. Set after processing a BD that has its I bit (interrupt) set.
20-8
Table 20-5. DCMR Field Descriptions
1 2
Ñ
0
R
IMMR + 0x910 (IDSR1); 0x918 (IDSR2)
Table 20-6. IDSR1/IDSR2 Field Descriptions
MPC860 PowerQUICC UserÕs Manual
Description
3 4
AD
R/W
Description
5 6
DONE OB
0 0
R/W R/W
MOTOROLA
7
0