Motorola MPC860 PowerQUICC User Manual page 261

Part II. PowerPC Microprocessor Module
Executing tlbia invalidates all entries in both TLBs, however if MI_CTR[RSV4I] or
MD_CTR[RSV4D] is set, the four reserved entries are not invalidated. Software can
explicitly invalidate one or more of these entries by setting MD_CTR[DTLB_INDX] or
MI_CTR[ITLB_INDX], negating MD_EPN[EV] or MI_EPN[EV], and writing to the
appropriate MD_RPN or MI_RPN. The TLBs are not invalidated automatically on reset,
but are disabled. However, they must be invalidated under program control during
initialization.
MOTOROLA Chapter 9. Memory Management Unit (MMU) 9-35