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software. In addition, there is no mechanism provided for DMA or other internal masters
to access the data cache directly.
The MPC860 data cache includes the following operational features:
¥ Single-cycle cache access on hit and one clock latency added for miss
¥ The data cache supports hits under load misses
¥ 1-word store buffer
¥ Store misses bypass the data cache (no-allocate store miss) in write-through mode
¥ 4-word copyback buffer holds replaced modiÞed cache blocks until they can be
written to memory
¥ Cache operation is blocked until the cache block is written to the cache array for
store misses in write-back mode,
¥ The data cache supports the sync instruction through a cache pipe clean indication
to the core.
8.6.1 Data Cache Load Hit
In the case of a data cache load hit, the requested word is transferred to the load/store unit.
The LRU state of the set is updated, but the state bits remain unchanged.The access time
for a data cache load hit is one clock cycle (that is, zero wait states).
8.6.2 Data Cache Read Miss
In the case of a data cache load miss, a block in the cache array is selected to receive the
data from memory. The selection algorithm gives Þrst priority to invalid blocks. If both
blocks in the set are marked invalid, the block in way 0 is selected. If neither of the two
blocks in the selected set are invalid, then the least recently used block is selected for
replacement. If the replacement block is marked modiÞed-valid, then it is temporarily
stored in a copyback buffer to be written to memory later. Locked cache blocks are never
replaced.
After a cache block has been selected, the word-aligned physical address of the requested
data is sent to the SIU with a 4-word burst transfer read request. The SIU arbitrates for the
bus and initiates the burst read. The transfer begins with the aligned word containing the
requested data (critical word Þrst), followed by the remaining words of the cache block (if
any), then by any remaining words at the beginning of the block (wrap-around).
The critical word is simultaneously written to the burst buffer and forwarded to the
load/store unit, thus minimizing stalls due to cache Þll latency. The data cache is not
blocked to internal accesses while the load (caused by a cache miss) completes. This
functionality is sometimes referred to as Ôhits under misses,Õ because the cache can service
a hit while a cache miss Þll is waiting to complete. If no bus errors are encountered during
the 4-word cache block load, the burst buffer is written to the cache array (provided the
cache array is not busy servicing a hit) and the cache block is marked unmodiÞed-valid.
MOTOROLA
Chapter 8. Instruction and Data Caches
Part II. PowerPC Microprocessor Module
8-25
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