Motorola MPC860 PowerQUICC User Manual page 203

Table 8-4. IC_ADR Fields for Cache Read Commands
0Ð17 18
Reserved 0 Tag
1 Data
To read the data or tags stored in the instruction cache:
1. Write the address of the data or tag to be read to the IC_ADR, according to the
format shown in Table 8-4.
Note that it is also possible to read this register for debugging purposes.
2. Read the IC_DAT register.
For data array (IC_ADR[18] = 0) read commands, the word selected by IC_ADR[28Ð29]
is placed in the target general-purpose register. For tag array (IC_ADR[18] = 1) read
commands, the tag and state information is placed in the target general-purpose register.
Table 8-5 provides the format of the IC_DAT register when reading a tag.
Table 8-5. IC_DAT Format when Reading a Tag
0Ð20 21
Tag value Reserved
8.3.1.2 IC_CST Commands
All IC_CST commands, except the load & lock cache block command, are executed
immediately after writing to the IC_CST register and do not generate any errors. Therefore,
when executing these commands there is no need to check the error type bits in the IC_CST
register. All commands should be followed by an isync instruction, if the instruction cache
command is required to affect all instruction fetches that come after it in the program order.
In addition, correct operation of the instruction cache relies on software following the
procedures described in Section 8.5.5, ÒUpdating Code And Memory Region Attributes.Ó
Note that when the instruction cache is executing a command, it stops handling CPU
requests, which can result in machine stalls.
8.3.1.2.1 Instruction Cache Enable/Disable Commands
The instruction cache enable command (IC_CST[CMD] = 0b001) is used to enable the
instruction cache; the instruction cache disable command (IC_CST[CMD] = 0b010) is used
to disable the instruction cache. Neither of these commands has any error cases. The current
state of the instruction cache is available by reading the instruction cache enable status bit
(IC_CST[IEN]).
When disabled, the MPC860 ignores the instruction cache valid bit and operates as if all
accesses have caching-inhibited access attributes (that is, all instruction fetches are
propagated to the bus as single-beat transactions). Disabling the instruction cache does not
MOTOROLA
19 20
0 Way 0 Reserved
1 Way 1
22
0 Invalid 0 Unlocked
1 Valid 1 Locked
Chapter 8. Instruction and Data Caches
Part II. PowerPC Microprocessor Module
21Ð27 28Ð29
Set select Word select
(0Ð127) (used only for
data array)
23 24
LRU bit of this set
30Ð31
Reserved
25Ð31
Reserved
8-9