Motorola MPC860 PowerQUICC User Manual page 297

Table 11-13 describes SWSR Þelds.
Bits Name
0Ð15 SEQ Sequence. This Þeld is the pattern that is used to control the state of the software watchdog timer.
11.8 The PowerPC Decrementer
A PowerPC-deÞned 32-bit decrementing counter supports the decrementer interrupt. In the
MPC860, the decrementer is clocked by TMBCLK, so TBSCR[TBE] must be set for the
decrementer to start. The timebase and decrementer counters are driven by TMBCLK:
The state of the decrementer is not affected by HRESET and SRESET, so it should be
initialized by software. Note, however, that it is disabled and reset by PORESET. It
continues counting while HRESET and SRESET are asserted and it is implemented with
the following requirements in mind.
¥ The decrementer is unaffected when read.
¥ When DEC[0] changes from 0 to 1, an interrupt request is signaled. If a previous
decrementer interrupt request was made, only one interrupt is reported.
¥ Explicitly changing DEC[0] from 0 to 1 in software signals an interrupt request.
A decrementer interrupt is also sent to the power-down wake-up logic, so the core can
waken from power-down mode. A decrementer exception causes a pending interrupt
request in the core, which is cleared automatically when the decrementer interrupt is taken,
Table 11-14 shows some decrementer periods available, assuming a 4-MHz oscillator.
Count Value
0
9
99
999
9999
11.8.1 Decrementer Register (DEC)
The decrementer register (DEC) is a PowerPC SPR. It can be read or written to by mfspr
or mtspr. DEC is powered by KAPWR and continues counting when KAPWR is applied.
Control of the decrementer is provided in the TBSCR. The decrementer and timebase use
TMBCLK. Note that DEC is a keyed register. It must be unlocked in TBK before it can be
written.
MOTOROLA
Table 11-13. SWSR Field Descriptions
T =
dec
Table 11-14. Decrementer Timeout Values
Timeout
1 ms
10. ms
100. ms
1.0 ms
10.0 ms
Chapter 11. System Interface Unit
Description
32
2
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( )
F
tmbclk
Count Value
999999
9999999
99999999
999999999
FFFFFFFF (hex)
Part III. Configuration
Timeout
1.0 s
10.0 s
100.0 s
1000. s
4295 s
11-23