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Illegal instructions. A class of instructions that are not implemented for a
Implementation. A particular processor that conforms to the PowerPC
Implementation-dependent. An aspect of a feature in a processorÕs design
Implementation-speciÞc. An aspect of a feature in a processorÕs design that
Imprecise exception. A type of synchronous exception that is allowed not to
Internal bus. The bus connecting the core and system interface unit (SIU).
Instruction latency. The total number of clock cycles necessary to execute
Interrupt. An asynchronous exception. On PowerPC processors, interrupts
L
Latency. The time an operation requires. For example, execution latency is
Least-signiÞcant bit (lsb). The bit of least value in an address, register, data
Least-signiÞcant byte (LSB). The byte of least value in an address, register,
MOTOROLA
particular PowerPC processor. These include instructions not deÞned
by
the
PowerPC
implementations, instructions that are deÞned only for 64-bit
implementations are considered to be illegal instructions. For 64-bit
implementations instructions that are deÞned only for 32-bit
implementations are considered to be illegal instructions.
architecture, but may differ from other architecture-compliant
implementations for example in design, feature set, and
implementation of optional features. The PowerPC architecture has
many different implementations.
that is deÞned by a processorÕs design speciÞcations rather than by
the PowerPC architecture.
is not required by the PowerPC architecture, but for which the
PowerPC architecture may provide concessions to ensure that
processors that implement the feature do so consistently.
adhere to the precise exception model (see Precise exception). The
PowerPC architecture allows only ßoating-point exceptions to be
handled imprecisely.
an instruction and make ready the results of that instruction.
are a special case of exceptions. See also asynchronous exception.
the number of processor clocks an instruction takes to execute.
Memory latency is the number of bus clocks needed to perform a
memory operation.
element, or instruction encoding.
data element, or instruction encoding.
Glossary of Terms and Abbreviations
architecture.
In
addition,
for
32-bit
Glossary--5
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