Motorola MPC860 PowerQUICC User Manual page 1025

Appendix C
Register Quick Reference Guide
C0
C0
This section provides a brief guide to the core registers.
C.1 PowerPC RegistersÑUser Registers
The MPC860 implements the user-level registers defined by the PowerPC architecture
except those required for supporting ßoating-point operations (the ßoating-point register
Þle (FPRs) and the ßoating-point status and control register (FPSCR)). User-level,
PowerPC registers are listed in Table C-1 and Table C-2. Table C-2 lists user-level
special-purpose registers (SPRs).
Description Name
General-purpose GPRs The thirty-two 32-bit (GPRs) are used for source
registers
Condition register
Table C-2 lists SPRs deÞned by the PowerPC architecture implemented on the MPC860.
SPR Number
Decimal SPR [5Ð9] SPR [0Ð4]
1 00000 00001
8 00000 01000
9 00000 01001
268 01000 01100
269 01000 01101
1
Extended opcode for mftb, 371 rather than 339.
2
Any write (mtspr) to this address causes an implementation-dependent software emulation exception.
MOTOROLA
Table C-1. User-Level PowerPC Registers
Comments
and destination operands.
CR See Section 5.1.1.1.1, ÒCondition Register
(CR).Ó
Table C-2. User-Level PowerPC SPRs
Name
XER See Section 5.1.1.1.3,
ÒXER.Ó
LR See the Programming
Environments Manual
CTR See the Programming
Environments Manual
1
TBL read Section 11.9, ÒThe
PowerPC Timebase.Ó
2
TBU read
Appendix C. Register Quick Reference Guide
Comments
Write: Full sync
Read: Sync relative to load/store operations
No
No
Write (as a store)
Access Level Serialize Access
User Ñ
User Only mtcrf
Serialize Access
C-1