Motorola MPC860 PowerQUICC User Manual page 570

Part V. The Communications Processor Module
Bit 0 1
Field
Reset
R/W
Addr
Bit 16 17 18
Field Ñ FRZ
Reset
R/W R R/W
Addr
Figure 20-3. SDMA Configuration Register (SDCR)
Table 20-2 describes the SDCR bit settings.
Bits Name
0Ð16 Ñ Reserved. Should be cleared.
17 FRZ Freeze. Recognize or ignore the freeze signal. If conÞgured to respond to the freeze signal, the
SDMA controller negates BR until freeze is negated or a reset occurs.
0 SDMA channels ignore the freeze signal.
1 SDMA channels respond to a freeze on the next bus cycle.
18Ð29 Ñ Reserved. Should be cleared.
30Ð31 RAID RISC controller (CP) arbitration ID. Sets the SDMAsÕ U-bus arbitration priority level. Should be
programmed to 0b01, priority level 5, for typical applications. (See Table 20-1 above.)
00 Priority level 6 (BR6).
01 Priority level 5 (BR5) (normal operation).
10 Priority level 2 (BR2).
11 Priority level 1 (BR1).
20.2.2 SDMA Status Register (SDSR)
Shared by all SDMA channels, the SDMA status register (SDSR) reports bus errors and
DSP events. When the SDMA controller recognizes an event, it sets the corresponding
event bit in the SDSR. SDSR bits are cleared by writing ones; writing zeros has no effect.
Figure 20-4 shows the register format.
Bit 0
Field SBER
Reset
R/W
Addr
20-4
2 3 4 5 6
0000_0000_0000_0000
19 20 21 22
Ñ
0000_0000_0000_0000
Table 20-2. SDCR Bit Settings
1 2
Figure 20-4. SDMA Status Register (SDSR)
MPC860 PowerQUICC UserÕs Manual
7 8 9 10
Ñ
R
IMMR + 0x030
23 24 25 26
AM
R
IMMR + 0x032
Description
3 4
Ñ
0000_0000
R/W
IMMR + 0x908
11 12 13 14
27 28 29 30
Ñ RAID
R/W
5 6
DSP2 DSP1
MOTOROLA
15
31
7