Motorola MPC860 PowerQUICC User Manual page 152

Part II. PowerPC Microprocessor Module
Operand
Byte
Half word
Word
Double word
Quad word
Note: An ÒxÓ in an address bit position indicates that the bit can be 0 or 1
independent of the state of other bits in the address.
The concept of alignment is also applied more generally to data in memory. For example,
a 12-byte data item is said to be word-aligned if its address is a multiple of four.
Any memory access that crosses an alignment boundary must be broken into multiple
discrete accesses. For the case of string accesses, the hardware makes no attempt to get
aligned in an effort to reduce the number of discrete accesses. (Multiword accesses are
architecturally required to be aligned.) The resulting performance degradation depends
upon how well each individual access behaves with respect to the memory hierarchy. At a
minimum, additional cache access cycles are required. More dramatically, for the case of
access to a noncacheable page, each discrete access involves an individual bus operation
which will reduce the effective bandwidth of the bus.
The frequent use of misaligned accesses is discouraged since they can compromise the
overall performance of the processor.
6.2 Instruction Set Summary
This section describes instructions and addressing modes deÞned for the MPC860. These
instructions are divided into the following functional categories:
¥ Integer instructionsÑThese include arithmetic and logical instructions. For more
information, see Section 6.2.4.1, ÒInteger Instructions.Ó
¥ Load and store instructionsÑThese include integer load and store instructions only.
For more information, see Section 6.2.4.2, ÒLoad and Store Instructions.Ó
¥ Flow control instructionsÑThese include branching instructions, condition register
logical instructions, and other instructions that affect the instruction ßow. For more
information, see Section 6.2.4.3, ÒBranch and Flow Control Instructions.Ó
¥ Trap instructionsÑThese instructions are used to test for a speciÞed set of
conditions; see Section 6.2.4.4, ÒTrap Instructions,Ó for more information.
¥ Processor control instructionsÑThese instructions are used for synchronizing
memory accesses and managing caches and TLBs. For more information, see
Sections 6.2.4.5, 6.2.5.1, and 6.2.6.2.
6-2
Table 6-1. Memory Operands
Length
8 bits
2 bytes
4 bytes
8 bytes
16 bytes
MPC860 PowerQUICC UserÕs Manual
Addr[28Ð31] If Aligned
xxxx
xxx0
xx00
x000
0000
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