Motorola MPC860 PowerQUICC User Manual page 276

Part III. Configuration
¥ Power management
¥ Real-time clock
¥ PowerPC decrementer
¥ Time base
¥ Periodic interrupt timer (PIT)
¥ External bus interface control
¥ Eight memory banks supported by the memory controller
¥ Debug support
¥ PCMCIA host adapter module supports two slots with eight memory or I/O
windows
¥ IEEE 1149.1 test access port
11.2 System ConÞguration and Protection
The MPC860 incorporates many system functions that normally must be provided in
external circuits. The following features provide maximum system safeguards against
hardware and/or software faults:
¥ System conÞgurationÑAllows control of parity checking, show cycle operation,
and part and mask number constants.
¥ Bus monitorÑMonitors the TA response time for bus accesses initiated by internal
masters. TEA is asserted if the TA response limit is exceeded. The bus monitor
measures time between TS and any termination of the bus cycle, including TA, TEA,
and RETRY.
¥ Software watchdog timerÑAsserts a reset or nonmaskable interrupt that is selected
by the system protection control register (SYPCR) if software fails to service this
timer after a certain period. After system reset, the timer, if enabled, selects a
maximum time-out period and asserts SRESET or NMI (system reset interrupt) if
the time-out is reached. This timer can be disabled or its time-out period can be
changed in SYPCR. Once SYPCR is written, it cannot be written again until a
system reset.
¥ Periodic interrupt timer (PIT)ÑGenerates periodic interrupts for use with a
real-time operating system (RTOS) or the application software. The PIT is clocked
by the PITRTCLK clock, thus providing a period from 122 microseconds to 8,000
mS assuming a 32.768-KHz crystal. The PIT can be disabled if it is not needed.
¥ PowerPC timebase counterÑProvides a timebase reference for the operating system
or application software. This 64-bit timebase counter is deÞned by the PowerPC
architecture and has two independent reference registers that generate a maskable
interrupt when the programmed value in one of the registers is reached. The
associated bit in the timebase status and control register (TBSCR) is set for the
reference register that generated the interrupt. The timebase is clocked by the
TMBCLK clock.
11-2 MPC860 PowerQUICC UserÕs Manual MOTOROLA