Motorola MPC860 PowerQUICC User Manual page 299

Table 11-16 describes TBU Þelds.
Bits Name
0Ð31 TBU Timebase upper. The value in this Þeld is used as an upper part of the timebase counter.
Figure 11-20 shows TBL.
Bit 0 1 2
Field
Reset
R/W
SPR
Figure 11-20. Timebase Lower Register (TBL)
Table 11-17 describes TBL Þelds.
Bits Name
0Ð31 TBL Timebase lower. The value in this Þeld is used as the lower part of the timebase register.
11.9.2 Timebase Reference Registers (TBREFA and TBREFB)
TBREFA and TBREFB are associated with TBU and TBL. When the contents of TBL
matches a reference register, a reference event is signaled in TBSCR[REFA] or
TBSCR[REFB]. These events can generate interrupts, if enabled. Note that TBREFA and
TBREFB are keyed registers. They must be unlocked in TBREFAK and TBREFBK before
they can be written.
Bit 0 1
Field
Reset
R/W
Addr TBREFA (IMMR & 0xFFFF0000) + 0x204/TBREFB (IMMR & 0xFFFF0000) + 0x208
Bit 16 17
Field
Reset
R/W
Addr TBREFA (IMMR & 0xFFFF0000) + 0x206/TBREFB (IMMR & 0xFFFF0000) + 0x20A
Figure 11-21. Timebase Reference Registers (TBREFA and TBREFB)
MOTOROLA
Table 11-16. TBU Field Descriptions
3 4 5 6
268 (Read)/284 (Write)
Table 11-17. TBL Field Descriptions
2 3 4 5
18 19 20 21 22
Chapter 11. System Interface Unit
Description
7 8 9
TBL
Ñ
R/W
Description
6 7 8 9 10
TBREFA/TBREFB
Ñ
R/W
23 24 25 26
TBREFA/TBREFB
Ñ
R/W
Part III. Configuration
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11 12 13 14 15
27 28 29 30 31
11-25
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