Motorola MPC860 PowerQUICC User Manual page 970

Part VI. Debug and Test
CORE
ICR
DER
9
BKPT, TE,
VSYNC
DSCK
DSDI
Figure 37-5. Functional Diagram of the MPC860 Debug Mode Support
The development port provides a full duplex serial interface for communications between
the internal development support logic of the core and an external development tool. The
development port can operate in two working modesÐtrap enable mode and debug mode.
Trap enable mode shifts the following control signals into the core internal development
support logic.
¥ Instruction trap enable bits for programming the instruction breakpoint dynamically.
¥ Load/store trap enable bits for programming the load/store breakpoint dynamically.
¥ Nonmaskable breakpoint is used to assert the nonmaskable external breakpoint.
¥ Maskable breakpoint is used to assert the maskable external breakpoint.
¥ VSYNC control code is used to assert and negate VSYNC operation.
In debug mode, the development port also controls the debug mode features of the core. See
Section 37.3.2, ÒDevelopment Port Communication.Ó
37-20
32
32
Development Port
Control Logic
DPIR
TECR DPDR
35
Development Port
Shift Register
MPC860 PowerQUICC UserÕs Manual
SIU / EBI
Internal
Bus
Development
Port Support
Logic
External
Bus
VFLS,
FRZ
DSDO
MOTOROLA