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Table 11-11 describes SIEL Þelds.
Bits
Name
0, 2, 4, 6,
EDn
Edge detect 0Ð7.
8, 10,
0 A low logical level in the IRQ signal indicates an interrupt request.
12, 14
1 A falling edge in the corresponding IRQ signal indicates interrupt request.
1, 3, 5, 7,
WMn
Wake-up mask 0Ð7
9, 11,
0 Not allowed to exit from low-power mode.
13, 15
1 Low-level detection in IRQn allows the MPC860 to exit or wake up from low-power mode.
16Ð31
Ñ
Reserved, should be cleared.
11.5.4.4 SIU Interrupt Vector Register (SIVEC)
The SIU interrupt vector register (SIVEC) is shown in Figure 11-13.
Bit
0
1
Field
Reset
R/W
Addr
Bit
16
17
Field
Reset
R/W
Addr
Figure 11-13. SIU Interrupt Vector Register (SIVEC)
Table 11-12 describes SIVEC Þelds.
Bits Name
0Ð7
INTC
Interrupt code. Indicates the highest priority pending interrupt; equals the interrupt number times 4, as
shown in Table 11-7.
8Ð31 Ñ
Reserved, should be cleared.
SIVEC[INTC] represents the unmasked interrupt source of the highest priority level. When
SIVEC is read as a byte, a branch table can be used in which each entry contains one
instruction (branch). The interrupt code is the interrupt number times 4, which allows
indexing into the table. When read as a half word, each entry can contain a full routine of
up to 256 instructions; see Figure 11-14 and Table 11-7.
MOTOROLA
Table 11-11. SIEL Field Descriptions
2
3
4
5
INTC
0011_1100_0000_0000
(IMMR & 0xFFFF0000) + 0x01C
18
19
20
21
22
0000_0000_0000_0000
(IMMR & 0xFFFF0000) + 0x01E
Table 11-12. SIVEC Field Descriptions
Chapter 11. System Interface Unit
Description
6
7
8
9
10
R
23
24
25
26
Ñ
R
Description
Part III. Configuration
11
12
13
14
15
Ñ
27
28
29
30
31
11-19
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