Motorola MPC860 PowerQUICC User Manual page 1076

Boundedly undeÞned. A characteristic of results of certain operations that
Breakpoint. A programmable event that forces the core to take a breakpoint
Burst. A bus transfer whose data phase consists of a sequence of transfers.
Bus parking. A feature that optimizes the use of the bus by allowing a device
C
Cache. High-speed memory component containing recently-accessed data
Cache coherency. An attribute in which an accurate and common view of
Cache ßush. An operation that removes from a cache any data from a
Caching-inhibited. A memory update policy in which the cache is bypassed
Cast-outs. Cache blocks that must be written to memory when a cache miss
Glossary--2
are not rigidly prescribed by the PowerPC architecture. Boundedly-
undeÞned results for a given operation may vary among
implementations, and between execution attempts in the same
implementation.
Although the architecture does not prescribe the exact behavior for
when results are allowed to be boundedly undeÞned, the results of
executing instructions in contexts where results are allowed to be
boundedly undeÞned are constrained to ones that could have been
achieved by executing an arbitrary sequence of deÞned instructions,
in valid form, starting in the state the machine was in before
attempting to execute the given instruction.
exception.
For example, on a 64-bit bus, a four-beat burst can transfer four,
64-bit double words.
to retain bus mastership without having to rearbitrate.
and/or instructions (subset of main memory).
memory is provided to all devices that share the a memory system.
Caches are coherent if a processor performing a read from its cache
is supplied with data corresponding to the most recent value written
to memory or to another processorÕs cache.
speciÞed address range. This operation ensures that any modiÞed
data within the speciÞed address range is written back to main
memory. This operation is generated typically by a Data Cache
Block Flush (dcbf) instruction.
and the load or store is performed to or from main memory.
causes a cache block to be replaced.
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