Motorola MPC860 PowerQUICC User Manual page 108

Part I. Overview
Name Type
IP_B5 Bidirectional Input Port B 5ÑThe MPC860 monitors this input; its value and changes are reported
LWP1
VF1
IP_B6 Bidirectional
DSDI Three-state
AT0
IP_B7 Bidirectional
PTR Three-state
AT3
OP[0Ð1] Output
OP2 Bidirectional Output Port 2ÑThis output is generated by the MPC860 as a result of a write to the
MODCK1
STS
OP3 Bidirectional Output Port 3ÑThis output is generated by the MPC860 as a result of a write to the
MODCK2
DSDO
BADDR30 Output
REG
3-10
Table 3-1. Signal Descriptions (Continued)
in the PIPR and PSCR of the PCMCIA interface.
Load/Store Watchpoint 1ÑThis output reports the detection of a data watchpoint in
the program ßow executed by the core.
Visible Instruction Queue Flushes StatusÑThe MPC860 outputs VF1 with VF0 and
VF2 when instruction ßow tracking is required. VFn reports the number of
instructions ßushed from the instruction queue in the core.
Input Port B 6ÑThe MPC860 senses this input and its value and changes are
reported in the PIPR and PSCR of the PCMCIA interface. See Chapter 17, ÒPCMCIA
Interface.Ó
Development Serial Data InputÑData input for the debug port interface. See
Chapter 37, ÒSystem Development and Debugging.Ó
Address Type 0ÑThe MPC860 drives this bidirectional three-state line when it
initiates a transaction on the external bus. If high (1), the transaction is the CPM. If
low (0), the transaction initiator is the CPU.
This signal is not used for transactions initiated by external masters.
Input Port B 7ÑThe MPC860 monitors this input; its value and changes are reported
in the PIPR and PSCR of the PCMCIA interface.
Program TraceÑTo allow program ßow tracking, the MPC860 asserts this output to
indicate an instruction fetch is taking place.
Address Type 3ÑThe MPC860 drives the bidirectional three-state signal when it
starts a transaction on the external bus. When the core initiates a transfer, AT3
indicates whether it is a reservation for a data transfer or a program trace indication
for an instruction fetch. AT3 is not used for transactions initiated by external masters.
Output Port 0Ð1ÑThe MPC860 generates these outputs as a result of a write to the
PGCRA register in the PCMCIA interface.
PGCRB register in the PCMCIA interface.
Mode Clock 1ÑInput sampled when PORESET is negated to conÞgure PLL/clock
mode.
Special Transfer StartÑThe MPC860 drives this output to indicate the start of an
external bus transfer or of an internal transaction in show-cycle mode.
PGCRB register in the PCMCIA interface.
Mode Clock 2ÑThis input is sampled at the PORESET negation to conÞgure the
PLL/clock mode of operation.
Development Serial Data OutputÑOutput data from the debug port interface.
Burst Address 30ÑThis output duplicates the value of A30 when the following is
true:
¥ An internal master in the MPC860 initiates a transaction on the external bus.
¥ An asynchronous external master initiates a transaction.
¥ A synchronous external master initiates a single beat transaction.
The memory controller uses BADDR30 to increment the address lines that connect
to memory devices when a synchronous external master or an internal master
initiates a burst transfer.
RegisterÑWhen an internal master initiates an access to a slave under control of the
PCMCIA interface, this signal duplicates the value of TSIZ0/REG. When an external
master initiates an access, REG is output by the PCMCIA interface (if it must handle
the transfer) to indicate the space in the PCMCIA card being accessed.
MPC860 PowerQUICC UserÕs Manual
Description
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