Motorola MPC860 PowerQUICC User Manual page 576

Part V. The Communications Processor Module
¥ The byte at (offset + 3) is the source function code register (SFCR). See
Section 20.3.4.1, ÒFunction Code RegistersÑSFCR and DFCR.Ó
¥ The word at (offset + 4) is the buffer length, containing the number of bytes for
transfer. It must be greater than zero.
¥ The word at (offset + 8) points to the beginning of the source buffer in internal or
external memory.
Ñ When the source is a peripheral, this Þeld is ignored in single-address mode. In
dual-address mode, this Þeld contains the peripheral address.
¥ The word at (offset + 0xC) points to the beginning of the destination buffer in
internal or external memory.
Ñ When the destination is a peripheral, this Þeld is ignored in single-address mode.
In dual-address mode, this Þeld contains the peripheral address.
Figure 20-8 shows the descriptor structure.
Offset 0 1
0x00 V Ñ
0x02
0x04
0x06
0x08
0x0A
0x0C
0x0E
Figure 20-8. IDMA Buffer Descriptor Structure
Table 20-7 describes an IDMA descriptorÕs status-and-control Þeld.
Bits Name
0 V Valid. Ready for processing.
0 Invalid. Not ready for transfer. The user can write to this descriptor and its buffer. When
buffer-chaining, the CP clears the V bit after the buffer has been transferred.
1 Valid for transfer. The user should not write to this descriptor or its buffer once the V bit is set.
Note: When an error condition is detected, the CP clears the V bit.
1 Ñ Reserved
2 W Wrap. Marks the end of the BD table.
0 Not the last descriptor in the BD table.
1 Last descriptor in the BD table. After this descriptor has been processed, the CP wraps the
current BD pointer (IBPTR) back to the top of the BD table (IBASE).
20-10
2 3 4 5
W I L Ñ CM
DFCR
Source Buffer Pointer
Destination Buffer Pointer
Table 20-7. IDMA BD Status and Control Bits
MPC860 PowerQUICC UserÕs Manual
6 7 8 9 10
Ñ Ñ Ñ Ñ
Buffer Length
Description
11 12 13 14 15
Ñ Ñ Ñ Ñ Ñ
SFCR
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