Motorola MPC860 PowerQUICC User Manual page 960

Part VI. Debug and Test
¥ A programmable AND-OR logic structure between the four instruction comparators
results in Þve outputs, four instruction watchpoints, and one instruction breakpoint.
¥ A programmable AND-OR logic structure between the four instruction watchpoints
and the four load/store comparators results in three outputs, two load/store
watchpoints, and one load/store breakpoint.
¥ Five watchpoint pins, three for instructions and two for loads/stores.
¥ Two dedicated 16-bit down counters. Each can count either an instruction
watchpoint or load/store watchpoint. Only architecturally executed events are
counted (count up is performed in case of recovery).
¥ On-the-ßy trap enable programming of the different internal breakpoints using the
development port serial interface (see Section 37.3.2, ÒDevelopment Port
CommunicationÓ). Software control is also available.
¥ Watchpoints do not change the timing of the machine.
¥ Internal breakpoints and watchpoints are detected on the instruction during fetch.
¥ Internal breakpoints and watchpoints are detected on the load/store during load/store
bus cycles.
¥ Instruction and load/store breakpoints and watchpoints are handled on retirement
and then reported.
¥ Breakpoints and watchpoints on recovered instructions (due to exceptions or missed
predictions) are not reported and do not change the machineÕs timing.
¥ Instructions with instruction breakpoints are not executed. The machine branches to
the breakpoint exception routine before it executes the instruction.
¥ Instructions with load/store breakpoints are executed. The machine branches to the
breakpoint exception routine after it executes the instruction. The address of the
access is placed in the BAR.
¥ Load/store multiple/string instructions with load/store breakpoints Þnish execution
before the machine branches to the breakpoint exception routine.
¥ Load/store data compare is accomplished on the load/store, after swap in store
accesses and before swap in load accesses (as the data appears on the bus).
¥ Internal breakpoints may operate either in masked mode or in nonmasked mode.
¥ ÒGo to xÓ and ÒcontinueÓ working modes are supported for instruction breakpoints.
37.2.2 Internal Watchpoints and Breakpoints Logic
Internal breakpoint and watchpoint support is based on the following:
¥ Eight comparators comparing information on instruction and load/store cycles
¥ Two counters
¥ Two AND-OR logic structures
37-10 MPC860 PowerQUICC UserÕs Manual MOTOROLA