Motorola MPC860 PowerQUICC User Manual page 201

BIT 0 1
FIELD IEN
RESET 0
R/W R
BIT 16 17
FIELD
RESET
R/W
SPR
Figure 8-3. Instruction Cache Control and Status Register (IC_CST)
Table 8-1 describes the bits of the IC_CST register.
Table 8-1. Instruction Cache Control and Status RegisterÑIC_CST
Bits Name
0 IEN Instruction cache enable status.
0
1
Note that this is a read-only bit. Any attempt to write to it is ignored.
1Ð3 Ñ Reserved
4Ð6 CMD Instruction cache command
000 Reserved
001 Cache enable
010 Cache disable
011 Load & lock cache block
100 Unlock cache block
101 Unlock all
110 Invalidate all
111 Reserved
Note that reading these bits always returns 0b000
7Ð9 Ñ Reserved
10 CCER1 Instruction cache error type 1Ñbus error during an IC_CST load & load cache block command
0
1
Note that this is a read-only, sticky bit, set only by the MPC860 when an error is detected.
Reading this bit clears it.
11 CCER2 Instruction cache error type 2Ñno unlocked way available for an IC_CST load & lock cache
block command
0
1
Note that this is a read-only, sticky bit, set only by the MPC860 when an error is detected.
Reading this bit clears it.
12 CCER3 Instruction cache error type 3Ñreserved.
13Ð31 Ñ Reserved
MOTOROLA
2 3 4 5
Ñ CMD
Ñ Ñ
Ñ R/W
18 19 20 21
The instruction cache is disabled
The instruction cache is enabled
No error detected
Error detected
No error detected
Error detected
Chapter 8. Instruction and Data Caches
Part II. PowerPC Microprocessor Module
6 7 8 9 10
CCER
Ñ
Ñ 0
Ñ R
22 23 24 25 26
Ñ
Ñ
Ñ
560
Description
11 12 13 14
CCER CCER
Ñ
1 2 3
0 0 Ñ
R R Ñ
27 28 29 30
15
31
8-7