The Mpc860 And The Powerpc Architecture - Motorola MPC860 PowerQUICC User Manual

Part II. PowerPC Microprocessor Module
When an lwarx instruction executes, the LSU issues a cycle to the data cache with a special
attribute. For external memory accesses, this attribute causes the external bus interface to
set a memory reservation during the address tenure. External logic must then snoop the
external bus to determine if another device breaks the memory reservation by accessing the
same location. KR and CR signals are available to external logic to signal loss of a
reservation to the external bus interface. When an stwcx. instruction addresses external
memory and the external bus interface determines that the reservation was lost, it blocks the
external bus access and notiÞes the LSU.
The MPC860 supports the memory reservation mechanism in a hierarchical bus structure.
For reservations on internal memory, an lwarx causes on-chip snoop logic to latch the
address. This logic notiÞes the LSU of any internal master store access and resets the
reservation. If a new lwarx instruction address tenure executes successfully, it replaces any
previous reservation address at the appropriate snoop logic. However, executing an stwcx.
instruction cancels the reservation unless an alignment exception is detected.

4.6 The MPC860 and the PowerPC Architecture

This section describes the relationship between the MPC860 and the PowerPC architecture.
It indicates the types of distinguishing features of the MPC860 described in the following:
¥ In many cases, the PowerPC architecture speciÞcation is ßexible enough to allow
implementation options. For example, the architecture does not specify whether
unaligned transfers must be handled in hardware or whether instruction execution
must be performed in hardware or software.
¥ The PowerPC architecture deÞnes optional features, some of which are
implemented on the MPC860 (such as TLBs) and some of which are not, such as the
eciwx and ecowx instructions.
¥ The PowerPC architecture deÞnes features, such as virtual memory and
ßoating-point instructions, that are not implemented on the MPC860.
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