Motorola MPC860 PowerQUICC User Manual page 704

Part V. The Communications Processor Module
Since the HDLC bus uses a wired-OR scheme, a transmitted zero has priority over a
transmitted 1. Figure 24-13 shows how CTS is used to detect collisions.
TCLK
TXD
(Output)
CTS
(Input)
Figure 24-13. Detecting an HDLC Bus Collision
If both the destination address and source address are included in the HDLC frame, then a
predeÞned priority of stations results; if two stations begin to transmit simultaneously, they
necessarily detect a collision no later than the end of the source address.
The HDLC bus priority mechanism ensures that stations share the bus equally. To minimize
idle time between messages, a station normally waits for eight one bits on the line before
attempting transmission. After successfully sending a frame, a station waits for 10 rather
than eight consecutive one bits before attempting another transmission. This mechanism
ensures that another station waiting to transmit acquires the bus before a station can
transmit twice. When a low priority station detects 10 consecutive ones, it tries to transmit;
if it fails, it reinstates the high priority of waiting for only eight ones.
24.14.3 Increasing Performance
Because it uses a wired-OR conÞguration, HDLC bus performance is limited by the rise
time of the one bit. To increase performance, give the one bit more rise time by using a
clock that is low longer than it is high, as shown in Figure 24-14.
24-20
CTS sampled at halfway point.
Collision detected when
TXD=1, but CTS=0.
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