Motorola MPC860 PowerQUICC User Manual page 985

address -4 must be written into GPR30. To end the download, an end download procedure
command should be issued to the debug port and an additional data transaction should be
sent by the development tool. This data word is not placed into system memory, but it is
needed to stop the procedure.
For large blocks of data this sequence may take a long time to complete. The fast download
procedure can reduce this time by eliminating the need to transfer instructions in the loop
to the debug port. The only transactions needed are those that transfer the data to be placed
in the system memory. Figure 37-13 shows the time beneÞt of the fast download procedure.
External
Transaction
Internal
Activity
External
Transaction
Internal
Activity
Figure 37-13. Fast and Slow Download Procedure Loops
37.4 Software Monitor Debugger Support
With debug mode disabled, a software monitor debugger can use the development support
features deÞned in the core; all events result in regular exception handling (the processor
resumes execution in the corresponding interrupt handler). The ICR and DER inßuence
only the assertion and negation of the freeze signal.
37.4.1 Freeze Indication
The internal freeze signal connects to all relevant internal modules, which can be
programmed to stop all operations in response to the assertion of the freeze signal. To
enable a software monitor debugger to broadcast the fact that debug software has executed,
it is possible to assert and negate the internal freeze signal when debug mode is disabled.
The assertion of the freeze signal is broadcast externally over FRZ. As shown in
Figure 37-6, the ICR and DER control assertion and negation of the freeze signal when
debug mode is disabled. To assert the freeze signal, software must program the relevant
DER bits, but to negate the freeze line, the software must read the ICR to clear it and
execute an rÞ. If the ICR is not cleared before the rÞ is executed, the freeze signal is not
negated. Therefore, it is possible to nest inside a software monitor debugger without
affecting the value of the freeze line, even though rÞ may execute a few times. Only before
the last rÞ instruction does software need to clear the ICR. The above mechanism allows
software to accurately control the assertion and negation of the freeze line.
MOTOROLA
MFSPR
Slow Download Procedure Loop Slow Download Procedure Loop
Fast Download Procedure Loop
Chapter 37. System Development and Debugging
DATA
DATA
Part VI. Debug and Test
STWU
37-35