Motorola MPC860 PowerQUICC User Manual page 953

37.1.2 Instruction Fetch Show Cycle Control
Instruction fetch show cycles are controlled by ICTRL[ISCT_SER] and the state of
VSYNC. Table 37-1 deÞnes the level of fetch show cycles generated by the core.
VSYN
ICTRL[ISCT_SER] Instruction Fetch Show Cycle Control Bits
C
X 000
X X01
X X10ÑEnable STS functionality of OP2/MODCK1/STS by writing
10 or 11 to SIUMCR[DBGC]. The external bus address should be
sampled only when STS is asserted.
0 X11
1 X11
A cycle marked with the program trace cycle attribute is generated when entering and
exiting VSYNC state by setting TECR[VSYNC].
37.1.3 Program Trace Signals
Note that if the MPC860 is in half-speed bus mode (SIUMCR[EBDF] = 01), the VF and
VFLS pins do not report fetch and ßush information for the program trace capability.
However, the internal freeze state of the processor is reported in the VFLS pins as it does
in full-speed bus mode. The status pins are divided into two groups, shown in Table 37-2.
Pins
VF [0Ð2] Instruction queue status. Denotes the type of the last fetched instruction or how many instructions were
ßushed from the instruction queue. VF [0Ð2] are used for both functions because queue ßushes occur
only in clocks in which no fetch type information is reported. Table 37-3 deÞnes instruction queue
ßushes and Table 37-4 deÞnes instruction fetch types.
VFLS [0Ð1] History buffer ßushes status: indicates the number of instructions that are ßushed from the history buffer
on this clock. Possible values are as follows:
00 None
01 1 instruction was ßushed from the history buffer
10 2 instructions were ßushed from the history buffer
11 Used for debug mode indication. Should be ignored by the program trace external hardware. See
Section 37.3.1, ÒDebug Mode Operation.Ó
Table 37-3 describes possible instruction queue ßushes as they are identiÞed by VF
encodings.
MOTOROLA
Table 37-1. Fetch Show Cycles Control
Table 37-2. Status Pin Groupings
Chapter 37. System Development and Debugging
Show Cycles Generated
All fetch cycles
All change of ßow (direct and
indirect)
All indirect change of ßow
No show cycles are performed
All indirect change of ßow
Description
Part VI. Debug and Test
37-3