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Bit
0
1
2
Field
Reset
R/W
Addr (IMMR & 0xFFFF0000) + 0x080 (PBR0); 0x088 (PBR1); 0x090 (PBR2); 0x098 (PBR3); 0x0A0 (PBR4); 0x0A8
Table 17-12 describes the PBR.
Bits Name
0Ð31
PBA PCMCIA base address. Compared to the address on the address bus to determine if a PCMCIA
window is being accessed by an internal bus master. PBA is used in conjunction with POR[BSIZE].
17.4.6 PCMCIA Option Register 0Ð7 (POR0ÐPOR7)
The POR, shown in Figure 17-8, as the manipulation of timing, provides the address mask
for the bank size, and deÞnes the region, slot, write protection, and validation.
Bit
0
1
2
Field
BSIZE
Reset
R/W
Addr
(IMMR & 0xFFFF0000) + 0x084 (POR0); 0x08C (POR1); 0x094 (POR2); 0x09C (POR3); 0x0A4 (POR4);
Bit
16
17
18
Field
PSST
Reset
R/W
Addr
(IMMR & 0xFFFF0000) + 0x086 (POR0); 0x08E (POR1); 0x096 (POR2); 0x09E (POR3); 0x0A6 (POR4);
Figure 17-8. PCMCIA Option Register 0Ð7 (POR0ÐPOR7)
MOTOROLA
3
4
5
(PBR5); 0x0B0 (PBR6); 0x0B8 (PBR7)
Figure 17-7. PCMCIA Base Register (PBR)
Table 17-12. PBR Field Descriptions
3
4
5
6
0x0AC (POR5); 0x0B4 (POR6); 0x0BC (POR7)
19
20
21
22
PSL
0x0AE (POR5); 0x0B6 (POR6); 0x0BE (POR7)
Chapter 17. PCMCIA Interface
É
PBA
Ñ
R/W
Description
7
8
9
10
Ñ
UndeÞned
R/W
23
24
25
26
PPS
PRS
UndeÞned
R/W
Part IV. Hardware Interface
11
12
13
14
PSHT
27
28
29
30
PSLOT
WP
31
15
31
PV
17-13
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