Motorola MPC860 PowerQUICC User Manual page 978

Part VI. Debug and Test
37.3.2.2.3 Development Port Registers Decode
The development port shift register is selected when the core accesses DPIR or DPDR.
Accesses to either register occur in debug mode and appears on the internal bus as an
address and the assertion of an address attribute signal indicating that an SPR is being
accessed. In debug mode, the core reads the DPIR to fetch all instructions; it reads and
writes to the DPDR to transfer data between the core and external development tools. DPIR
and DPDR are pseudo-registers; decoding either causes the development port shift register
to be accessed. Debug mode logic knows whether the core is fetching instructions or
reading or writing data. A sequence error is signaled to the external development tool when
the core expected result and the GPR results do not match, for example if an instruction is
received when data is expected.
37.3.2.3 Development Port Serial CommunicationsÐClock Mode
All development port serial transmissions are synchronous communications. The
development port supports two ways to clock serial transmissions.
37.3.2.3.1 Asynchronous Clocked ModeÑUsing DSCK
The Þrst clock mode is called asynchronous clocked since the input clock DSCK is
asynchronous with CLKOUT. To ensure that data on DSDI is sampled correctly, transitions
on DSDI must meet all setup and hold times with respect to the rising edge of DSCK. This
clock mode allows communications with the port from a development tool which does not
have access to CLKOUT or where CLKOUT has been delayed or skewed. Figure 37-9
shows the serial communications asynchronous clocked timing.
DSCK
DSDI
DSDO READY
Debug port drives the ÒreadyÓ bit onto DSDO when ready for a new transmission.
NOTE: DSCK and DSDI transitions are not required to be synchronous with CLKOUT.
Figure 37-9. Asynchronous Clocked Serial Communications
37-28
START MODE CNTRL
S<0> S<1>
Debug Port detects the ÒstartÓ bit on DSDI and follows the
ÒreadyÓ bit with two status bits and 7 or 32 output data bits.
Development Tool drives the ÒstartÓ bit on DSDI (after detecting the ÒreadyÓ bit
on DSDO when in debug mode). The Òstart bit is immediately followed by a
mode bit and a control bit and then 7 or 32 input data bits.
MPC860 PowerQUICC UserÕs Manual
DI<0> DI<N-2> DI<N-1> DI<N>
DO<0> DO<N-2>DO<N-1> DO<N>
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