Motorola MPC860 PowerQUICC User Manual page 909

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35.5.1 CPM Interrupt ConÞguration Register (CICR)
The CPM interrupt conÞguration register (CICR) deÞnes CPM interrupt request levels, the
priority between the SCCs, and the highest priority interrupt.
Figure 35-3. CPM Interrupt Configuration Register (CICR)
Bit
0
1
Field
Reset
R/W
Address
Bit
16
17
Field
IRL
Reset
R/W
Add
CICR bits are described in Table 35-3.
Bits
Name
0Ð7
Ñ
Reserved, should be cleared.
1
8Ð9
SCdP
SCCd priority order. DeÞnes which SCCs asserts its request in the SCCd priority position.
00 SCC1 asserts its request in the SCCd position.
01 SCC2 asserts its request in the SCCd position.
10 SCC3 asserts its request in the SCCd position.
11 SCC4 asserts its request in the SCCd position.
1
10Ð11 SCcP
SCCc priority order. DeÞnes which SCCs asserts its request in the SCCc priority position.
00 SCC1 asserts its request in the SCCc position.
01 SCC2 asserts its request in the SCCc position.
10 SCC3 asserts its request in the SCCc position.
11 SCC4 asserts its request in the SCCc position.
1
12Ð13 SCbP
SCCb priority order. DeÞnes which SCCs that asserts its request in the SCCb priority position.
00 SCC1 asserts its request in the SCCb position.
01 SCC2 asserts its request in the SCCb position.
10 SCC3 asserts its request in the SCCb position.
11 SCC4 asserts its request in the SCCb position.
1
14Ð15 SCaP
SCCa priority order. DeÞnes which SCCs that asserts its request in the SCCa priority position.
00 SCC1 asserts its request in the SCCa position.
01 SCC2 asserts its request in the SCCa position.
10 SCC3 asserts its request in the SCCa position.
11 SCC4 asserts its request in the SCCa position.
16Ð18 IRL
Interrupt request level. Contains the priority request level of the interrupt from the CPM that is sent to
the SIU. Level 0 indicates highest priority. IRL is initialized to zero during reset. In most systems,
value 0b100 is a good value to choose for IRL.
MOTOROLA
2
3
4
5
Ñ
0000_0000_0000_0000
18
19
20
21
22
HP
0000_0000_0000_0000
Table 35-3. CICR Field Descriptions
Chapter 35. CPM Interrupt Controller
Part V. The Communications Processor Module
6
7
8
9
10
SCdP
R/W
0x940
23
24
25
26
IEN
R/W
0x942
Description
11
12
13
14
SCcP
SCbP
SCaP
27
28
29
30
Ñ
15
31
SPS
35-7

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