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Part V. The Communications Processor Module
Table 26-1. Asynchronous HDLC-Specific SCC Parameter RAM Memory Map
1
Offset
Name
Width
0x48
Ñ
Hword Reserved
0x4A
RFTHR
Hword Received frames threshold. Number of Rx frames needed to trigger SCCE[RXF]
0x4C
Ñ
Word
0x50
TXCTL_TBL Word
0x54
RXCTL_TBL Word
0x58
NOF
Hword Number of opening ßags to be sent at the beginning of a frame. A value of n
0x5A
Ñ
Hword Reserved
1
From SCC base. SCC base = IMMR + 0x3C00 (SCC1) or 0x3D00 (SCC2) or 0x3E00 (SCC3) or 0x 3F00 (SCC4)
Figure 26-3 shows bit arrangements for TXCTL_TBL and RXCTL_TBL.
0
1
2
0x1F 0x1E 0x1D 0x1C 0x1B 0x1A 0x19 0x18 0x17 0x16 0x15 0x14 0x13 0x12 0x11 0x10
16
17
18
0x0F 0x0E 0x0D 0x0C 0x0B 0x0A 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00
26.9 ConÞguring GSMR and DSR for Asynchronous
HDLC
General SCC parameters can be conÞgured as described in Chapter 22, ÒSerial
Communications Controllers,Ó except for the following changes:
26.9.1 General SCC Mode Register (GSMR)
Table 26-2 shows asynchronous HDLC-speciÞc information for the GSMR.
26-6
Reserved
Control character tables. Stores the bit array used for the Tx/Rx control characters.
See Figure 26-3. Each bit corresponds to a character that should be mapped
according to RFC 1549. If a TXCTL_TBL bit is set, its corresponding character is
mapped; otherwise, it is not mapped. If an RXCTL_TBL bit is set, its corresponding
character is discarded if received; otherwise, it is received normally. TXCTL_TBL
and RXCTL_TBL should be initialized to zero for IrLAP.
corresponds to n+1 ßags.
3
4
5
6
19
20
21
22
Figure 26-3. TXCTL_TBL/RXCTL_TBL
MPC860 PowerQUICC UserÕs Manual
Description
7
8
9
10
23
24
25
26
11
12
13
14
27
28
29
30
MOTOROLA
15
31
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