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17.2.1 PCMCIA Cycle Control Signals
Table 17-1 describes PCMCIA cycle control signals.
Signal
A[6Ð31]
Address bus. Output. A[6Ð31] should be buffered to generate the socket signals. A[25Ð0]. These address
bus output lines allow direct addressing of up to 64 Mbytes of memory on each PCMCIA card. A6 is the
msb.
REG
Attribute memory select. Output. When REG is asserted during a PCMCIA access, card access is limited
to attribute memory when a memory access occurs (WE or OE are asserted) and to I/O ports when an I/O
access occurs (IORD or IOWR are asserted). If REG is asserted, accesses to common memory or DMA
devices are blocked. When no PCMCIA access is performed, this signal is TSIZ0.
CE1_x,
Card enable. Output. When a PCMCIA access is performed, CE1 enables even bytes; CE2 enables odd
CE2_x
bytes, as shown below.
D[0Ð15]
Data bus. Bidirectional. D[0Ð15] constitute the bidirectional data bus. The msb is D0 and the lsb is D15.
WAIT_
Extend bus cycle. Input. Asserted by the PC card to delay completion of the pending memory or I/O cycle.
R/W
External transceiver direction. Output. Asserted during MPC860 read cycles and negated (driven low)
during write cycles. Used in the PCMCIA interface to control the direction of the data bus transceivers.
IORD_
I/O read. Output. During PCMCIA accesses, this signal is asserted together with REG_x and it is used to
read data from the PC card I/O space. IORD_x is valid only when the REG_x and at least one of the CE1_x
and CE2_x signals is also asserted.
IOWR_
I/O write. Output. Asserted with REG_x during PCMCIA accesses used to latch data into the PC card I/O
space. Valid only when REGx and either or both CE1_x and CE2_x signals are also asserted.
OE_x
Output enable. Output. During PCMCIA accesses, OE_x is used to drive memory read data from a PC
card in a PCMCIA socket.
WE_x
Write enable/program. Output. During PCMCIA accesses, WE_x is used to latch memory write data to the
PC card in a PCMCIA socket. Can also be used as the programming strobe for PC cards using
programmable memory technologies.
MOTOROLA
Table 17-1. PCMCIA Cycle Control Cycles
Port Size
Access Size
8 bits
16-bit (even only)
8-bit odd
8-bit even
16 bits
16-bit (even only)
8-bit odd
8-bit even
No access
Chapter 17. PCMCIA Interface
Description
MPC860:A31 (Slot: A0)
0
1
0
0
1
0
X
Part IV. Hardware Interface
CE2
CE1
1
0
1
0
1
0
0
0
0
1
1
0
1
1
17-3
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