Motorola MPC860 PowerQUICC User Manual page 423

Table 15-8. SCCR Field Descriptions (Continued)
Bits Name
21Ð23 DFNL Division factor low frequency. Sets the VCOOUT frequency division factor for general system clocks
to be used in low-power mode. In low-power mode, the MPC860 automatically switches to the
DFNL frequency. To select the DFNL frequency, load this Þeld with the divide value and set the
CSRC bit. A loss-of-lock condition will not occur when you change the value of this Þeld. This Þeld is
cleared by a power-on or hard reset.
000 = Divide by 2.
001 = Divide by 4.
010 = Divide by 8.
011 = Divide by 16.
100 = Divide by 32.
101 = Divide by 64.
110 = Reserved.
111 = Divide by 256.
24Ð26 DFNH Division factor high frequency. Sets the VCOOUT frequency division factor for general system
clocks to be used in normal mode. In normal mode, the MPC860 automatically switches to the
DFNH frequency. To select the DFNH frequency, load this Þeld with the divide value and clear
CSRC. A loss-of-lock condition does not occur when this Þeld is changed. This Þeld is cleared by a
power-on or hard reset.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Reserved.
27Ð31 Ñ Reserved, should be cleared.
15.6.2 PLL, Low-Power, and Reset Control Register (PLPRCR)
The 32-bit system PLL, low-power, and reset control register (PLPRCR) is powered by a
keep-alive power supply and is used to control the system frequency and low-power mode
operation.
MOTOROLA Chapter 15. Clocks and Power Control
Part IV. Hardware Interface
Description
15-29