Motorola MPC860 PowerQUICC User Manual page 1011

Table A-3. Little-Endian Program/Data Path Between the
Fetch/ U-bus
Little-
Load
Endian
Store Cache
Addr
Type Addr
Word 0
Half-word 0
Half-word 2
Byte 0
Byte 1
Byte 2
Byte 3
Table A-4. Little-Endian Program/Data Path Between the
Fetch/ U-bus
Little-
Load
Endian
Store Cache
Addr
Type Addr
Word 0
Half-word 0
Half-word 2
Byte 0
Byte 1
Byte 2
Byte 3
MOTOROLA
Register and 32-Bit Memory
Data in the
Register
External
and
Bus
M
Addr
S
B
0 0 11 12 13 14 11 12 13 14 14 13 12 11 11 12 13 14
2 0
0 2
3 0
2 1
1 2
0 3
Register and 16-Bit Memory
Data in the
Register
External
and
Bus
M
Addr
S
B
0 0 11 12 13 14 11 12 13 14 14 13
2
2 0
0 2
3 0
2 1
1 2
0 3
Appendix A. Byte Ordering
U-bus and
Cache Format
L
S 0 1 2 3
B
21 22 21 22 22 21
31 32 31 32
ÔaÕ ÔaÕ ÔaÕ
ÔbÕ ÔbÕ
ÔcÕ ÔcÕ
ÔdÕ ÔdÕ
U-bus and
Cache format
L
S 0 1 2 3
B
21 22 21 22 22 21
31 32 31 32
ÔaÕ ÔaÕ ÔaÕ
ÔbÕ ÔbÕ
ÔcÕ ÔcÕ
ÔdÕ ÔdÕ
Appendixes
External Bus Little-Endian
Format Program/Data
0 1 2 3 3 2
32 31 31 32
ÔbÕ
ÔcÕ ÔcÕ
ÔdÕ ÔdÕ
External Bus Little-Endian
Format Program/Data
0 1 2 3 3 2
12 11
32 31
ÔbÕ
ÔcÕ
ÔdÕ
1 0
21 22
ÔaÕ
ÔbÕ
1 0
13 14
11 12
21 22
31 32
ÔaÕ
ÔbÕ
ÔcÕ
ÔdÕ
A-5