Motorola MPC860 PowerQUICC User Manual page 283

11.4.3 System Protection Control Register (SYPCR)
The system protection control register (SYPCR) controls the system monitors and bus
monitor timing. It can be read at any time, but can be written only once after system reset.
Bit 0 1
Field
Reset
R/W
SPR
Bit 16 17 18
Field
Reset
R/W
SPR
Figure 11-4. System Protection Control Register (SYPCR)
Table 11-4 describes SYPCR Þelds.
Bits Name
0Ð15 SWTC Software watchdog timer count. Count value for the software watchdog timer.
16Ð23 BMT Bus monitor timing. DeÞnes the timeout period, in 8 system clock resolution, for the bus monitor.
maximum timeout is 2,040 clocks.
24 BME Bus monitor enable. Controls bus monitor operation during internal-to-external bus cycles.
0 Disable the bus monitor.
1 Enable the bus monitor.
Note: If the bus monitor is disabled, transfer error conditions do not cause TEA to be asserted.
28 SWF Software watchdog freeze
0 The software watchdog timer continues counting even if FRZ is asserted.
1 The software watchdog timer stops counting when FRZ is asserted.
29 SWE Software watchdog enable.
To disable the software watchdog timer, it should be cleared by the software after a system reset.
0 Software watchdog timer disabled.
1 Software watchdog timer enabled.
30 SWRI Software watchdog reset/interrupt select.
0 The software watchdog timer causes an NMI (system reset interrupt) to the core.
1 The software watchdog timer causes an HRESET (default).
31 SWP Software watchdog prescale.
0 The software watchdog timer is not prescaled.
1 The software watchdog timer is prescaled by a factor of 2,048.
MOTOROLA
2 3 4 5 6
1111_1111_1111_1111
(IMMR & 0xFFFF0000) + 0x004
19 20 21 22
BMT
1111_1111
(IMMR & 0xFFFF0000) + 0x006
Table 11-4. SYPCR Field Descriptions
Chapter 11. System Interface Unit
7 8 9 10 11
SWTC
R/W
23 24 25 26 27
BME Ñ
0 000
R/W
Description
Part III. Configuration
12 13 14 15
28 29 30 31
SWF SWE SWRI SWP
0 1 1 1
11-9