Motorola MPC860 PowerQUICC User Manual page 971

37.3.1 Debug Mode Operation
Figure 37-6 shows the debug mode logic implemented in the core.
RFI
Debug Mode Enable
The debug mode of the core provides the development system with the following functions:
¥ Controls and maintains execution of the processor in all circumstances. The
development port can force the core to enter debug mode even when external
interrupts are disabled.
¥ Debug mode can be entered immediately out of reset, allowing the user to debug a
system without using ROM.
¥ The debug enable register (DER) can be used to selectively enable events that cause
the machine to enter debug mode.
¥ The interrupt cause register (ICR) indicates why debug mode is entered.
¥ After entry into debug mode, program execution continues from the where debug
mode was entered.
¥ All instructions are fetched from the development port, while load/store accesses are
performed on the real system memory in debug.
MOTOROLA
Decoder
Interrupt Cause Register (ICR)
Debug Enable Register (DER)
Reset Set
Q
Figure 37-6. Debug Mode Logic Diagram
Chapter 37. System Development and Debugging
Event (Core Interrupt
5
Or Exception)
Event Valid
Internal Debug
Mode Signal
Part VI. Debug and Test
Freeze
ICR_OR
37-21