Motorola MPC860 PowerQUICC User Manual page 440

Part IV. Hardware Interface
Bit 0 1 2
Field
Reset
R/W
Addr
Bit 16 17 18
Field G0CLx
Reset 000
R/W
Addr
Figure 16-10. Machine A Mode Register/Machine B Mode Registers (MxMR)
Table 16-6 describes bits for MAMR/MBMR.
Bits Name
0Ð7 PTx Periodic timer x period. Affects periodic timer x and determines the timer period service rate
according to the following equation, which determines value for UPMx to refresh memory:
NCS is an integer between 1 and 8 that represents the number of enabled chip selects that are
serviced by this UPM. SCCR[DFBRG] is deÞned in Section 15.6.1, ÒSystem Clock and Reset
Control Register.Ó For example, for DRAM to maintain data integrity, an access or refresh must
occur every 15.6 ms. Given a 25-MHz system clock with the required service rate of 15.6 ms, a
periodic timer prescaler = 32, and DFBRG = 0, PTx = (25 ´ 15.6) / (2
8 PTxE Periodic timer x enable. Allows the periodic timer x to request service.
0 Periodic timer x is disabled.
1 Periodic timer x is enabled.
9Ð11 AMx Address multiplex size x. When internal address multiplexing is used, this Þeld speciÞes how the
address on the external bus is multiplexed, when enabled (see Table 16-17). The SAM bit
enables address multiplexing in the Þrst clock cycle. The AMx Þeld of the RAM array entry
enables address multiplexing in subsequent clock cycles. (see Table 16-18).
12 Ñ Reserved, should be cleared.
13Ð14 DSx Disable timer period. Guarantees a minimum time between accesses to the same memory bank
if it is controlled by the UPMx. This function can be used to guarantee a minimum RAS
precharge time. The TODT bit in the RAM array turns on the disable timer and, when expired,
the UPMx allows the machine access to issue a memory pattern to the same region. An access
attempted before the timer expires (as signalled by TS assertion) has wait states inserted before
the UPM pattern runs. Accesses to other chip-selects serviced by this UPM are unaffected by
this timer. The maximum disable period is four clock cycles. If more than 4 cycles are required,
they must be added explicitly in the UPM RAM words.
00 1-cycle disable period
01 2-cycle disable period
10 3-cycle disable period
11 4-cycle disable period
15 Ñ Reserved, should be cleared.
16-14
3 4 5
PTx
0000_0000_0000_0000
(IMMR & FFFF0000) + 0x170
19 20 21
GPLx4DIS RLFx
1 0000
(IMMR & FFFF0000) + 0x172
Table 16-6. MxMR Field Descriptions
System Clock (MHz) Service Duration (ms)
PTx = -------------------------------------------------------------------------------------------------------------------- -
´
2 [
SCCR DFBRG
2
MPC860 PowerQUICC UserÕs Manual
6 7 8 9
PTxE AMx
R/W
22 23 24 25
WLFx
0000
R/W
Description
´
]
´ ´
Prescaler (PTP) NCS
10 11 12 13 14
Ñ DSx
26 27 28 29 30
TLFx
0000
2´0
´ 32´ 1) = 12.
MOTOROLA
15
Ñ
31