Motorola MPC860 PowerQUICC User Manual page 648

Part V. The Communications Processor Module
22.3.1 Function Code Registers (RFCR and TFCR)
Each SCC has two separate function code registersÑone for Rx buffers (RFCRx) and one
for Tx buffers (TFCRx). Function code registers contain the value to appear on AT[1Ð3]
when the associated SDMA channel accesses memory. It also selects the byte-ordering
convention. Figure 22-8 shows the register format.
Bit 0
Field
Reset
R/W
Addr
Figure 22-8. Function Code Registers (RFCR and TFCR)
Table 22-5 describes RFCRx/TFCRx Þelds.
Table 22-5. RFCRx /TFCRx Field Descriptions
Bits Name
0Ð2 Ñ Reserved, should be cleared.
3Ð4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the
beginning of the next BD. See Appendix A, ÒByte Ordering.Ó
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
5Ð7 AT[1Ð3] Address type. Contains the function code value used during the SDMA channel memory access.
Note AT[0] is driven high to identify this SDMA channel access as a DMA type.
22.3.2 Handling SCC Interrupts
SCC interrupts are handled globally by the CPM interrupt controller (CPIC) using the CPM
interrupt pending register (CIPR), CPM interrupt mask register (CIMR), and CPM
in-service register (CISR), described in Chapter 35, ÒCPM Interrupt Controller.Ó Bits in
each CPIC register are used to mask, enable, or report individual interrupts in an SCC
channel. Interrupt priority among SCCs is determined in the CPM interrupt conÞguration
register (CICR).
To allow interrupt handling for SCC-speciÞc events, further event, mask, and status
registers are provided within each SCCÕs internal memory map area; see Table 22-6. Since
interrupt events are protocol-dependent, event descriptions are found in the speciÞc
protocol chapters.
22-16
1 2
Ñ
0000_0000_0000_0000
SCCx base + 0x04 (RFCRx); SCCx base + 0x05 (TFCRx)
MPC860 PowerQUICC UserÕs Manual
3 4 5
BO
R/W
Description
6 7
AT[1Ð3]
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