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DOCUMENT NUMBER
9S12DT256DGV3/D
MC9S12DT256
Device User Guide
V03.07
Covers also
MC9S12A256, MC9S12DJ256
MC9S12DG256,
Original Release Date: 24 March 2003
Revised: 12 October 2005
Motorola, Inc
Motorola reserves the right to make changes without further notice to any products herein to improve reliability, function or
design. Motorola does not assume any liability arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
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   Summary of Contents for Motorola MC9S12DT256

  • Page 1

    Motorola product could create a situation where personal injury or death may occur.

  • Page 2

    Motorola product could create a situation where personal injury or death may occur.

  • Page 3

    MC9S12DT256 Device User Guide — 9S12DT256DGV3/D V03.07...

  • Page 4

    MC9S12DT256 Device User Guide — 9S12DT256DGV3/D V03.07...

  • Page 5: Table Of Contents

    MC9S12DT256 Device User Guide — V03.07 Table of Contents Section 1 IntroductionMC9S12DT256 Overview.............19 Features .

  • Page 6

    MC9S12DT256 Device User Guide — V03.07 2.3.21 PH7 / KWH7 / SS2 — Port H I/O Pin 7 ........61 2.3.22...

  • Page 7

    MC9S12DT256 Device User Guide — V03.07 2.3.57 PS0 / RXD0 — Port S I/O Pin 0 .........66 2.3.58...

  • Page 8

    MC9S12DT256 Device User Guide — V03.07 CPU12 Block Description ..........79 HCS12 Module Mapping Control (MMC) Block Description .

  • Page 9

    MC9S12DT256 Device User Guide — V03.07 Appendix A Electrical Characteristics General............. .89 A.1.1...

  • Page 10

    MC9S12DT256 Device User Guide — V03.07...

  • Page 11

    MC9S12DT256 Block Diagram ........23...

  • Page 12

    MC9S12DT256 Device User Guide — V03.07...

  • Page 13

    MC9S12DT256 Device User Guide — V03.07 List of Tables Table 0-1 Derivative Differences ..........15 Table 0-2 Document References .

  • Page 14

    MC9S12DT256 Device User Guide — V03.07 Table A-21 Expanded Bus Timing Characteristics ....... .125...

  • Page 15: Figure 0-1 Order Partnumber Example

    MC9S12DT256 Device User Guide — V03.07 Derivative Differences and Document References Derivative Differences Table 0-1 shows the availability of peripheral modules on the various derivatives. For details about the compatibility within the MC9S12D-Family refer also to engineering bulletin EB386. Table 0-1 Derivative Differences...

  • Page 16

    MC9S12DT256 Device User Guide — V03.07 The following items should be considered when using a derivative (Table 0-1): • Registers – Do not write or read CAN0 registers (after reset: address range $0140 - $017F), if using a derivative without CAN0.

  • Page 17: Table 0-2 Document References

    MC9S12DT256 Device User Guide — V03.07 The Device Guide provides information about the MC9S12DT256 device made up of standard HCS12 blocks and the HCS12 processor core. This document is part of the customer documentation. A complete set of device manuals also includes the HCS12 Core User Guide and all the individual Block Guides of the implemented modules.

  • Page 18

    MC9S12DT256 Device User Guide — V03.07 Table 0-3 Specification Change Summary for Maskset L91N Block Spec Change EETS4K/FTS256K Reliability Specification for Non Volatile Memories PIM_9DP256 CAN0 can be routed to PORTJ...

  • Page 19: Section 1 Introductionmc9s12dt256

    I/O lines with interrupt and wakeup capability, three CAN 2.0 A, B software compatible modules (MSCAN12), and an Inter-IC Bus. The MC9S12DT256 has full 16-bit data paths throughout. However, the external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems.

  • Page 20

    MC9S12DT256 Device User Guide — V03.07 – Programmable rising or falling edge trigger • Memory – 256K Flash EEPROM – 4K byte EEPROM – 12K byte RAM • Two 8-channel Analog-to-Digital Converters – 10-bit resolution – External conversion trigger capability •...

  • Page 21: Modes Of Operation

    MC9S12DT256 Device User Guide — V03.07 – Compatible with I2C Bus standard – Multi-master operation – Software programmable for one of 256 different serial clock frequencies • 112-Pin LQFP package – I/O lines with 5V input and drive capability – 5V A/D converter inputs –...

  • Page 22: Block Diagram

    MC9S12DT256 Device User Guide — V03.07 1.4 Block Diagram Figure 1-1 shows a block diagram of the MC9S12DT256 device.

  • Page 23: Figure 1-1 Mc9s12dt256 Block Diagram

    MC9S12DT256 Device User Guide — V03.07 Figure 1-1 MC9S12DT256 Block Diagram 256K Byte Flash EEPROM ATD0 ATD1 VDDA VDDA VDDA 12K Byte RAM VSSA VSSA VSSA PAD00 PAD08 4K Byte EEPROM PAD01 PAD09 PAD02 PAD10 VDDR PAD03 PAD11 VSSR PAD04...

  • Page 24: Device Memory Map

    MC9S12DT256 Device User Guide — V03.07 1.5 Device Memory Map Table 1-1 and Figure 1-2 show the device memory map of the MC9S12DT256 after reset. Note that after reset the bottom 1k of the EEPROM ($0000 - $03FF) are hidden by the register space.

  • Page 25

    MC9S12DT256 Device User Guide — V03.07 Table 1-1 Device Memory Map Size Address Module (Bytes) $1000 - $3FFF RAM array 12288 Fixed Flash EEPROM array $4000 - $7FFF 16384 incl. 0.5K, 1K, 2K or 4K Protected Sector at start $8000 - $BFFF Flash EEPROM Page Window...

  • Page 26: Figure 1-2 Mc9s12dt256 Memory Map

    MC9S12DT256 Device User Guide — V03.07 Figure 1-2 MC9S12DT256 Memory Map $0000 $0000 REGISTERS $0400 (Mappable to any 2k Block within the first 32K) $03FF $0000 4K Bytes EEPROM $1000 (Mappable to any 4K Block) $0FFF $1000 12K Bytes RAM...

  • Page 27: Detailed Register Map

    MC9S12DT256 Device User Guide — V03.07 1.6 Detailed Register Map The following tables show the detailed register map of the MC9S12DT256. $0000 - $000F MEBI map 1 of 3 (Core User Guide) Address Name Bit 7 Bit 6 Bit 5...

  • Page 28

    MC9S12DT256 Device User Guide — V03.07 $0010 - $0014 MMC map 1 of 4 (Core User Guide) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0012 INITEE EE15 EE14...

  • Page 29

    MC9S12DT256 Device User Guide — V03.07 $001E - $001E MEBI map 2 of 3 (Core User Guide) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $001E IRQE IRQEN INTCR...

  • Page 30

    MC9S12DT256 Device User Guide — V03.07 $0028 - $002F BKP (Core User Guide) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $002D BKP1X BK1V5 BK1V4 BK1V3 BK1V2 BK1V1 BK1V0...

  • Page 31

    MC9S12DT256 Device User Guide — V03.07 $0034 - $003F CRG (Clock and Reset Generator) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FORBYP Read: $003D RTIBYP COPBYP PLLBYP TEST ONLY...

  • Page 32

    MC9S12DT256 Device User Guide — V03.07 $0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0053 TC1 (lo) Bit 7...

  • Page 33

    MC9S12DT256 Device User Guide — V03.07 $0040 - $007F ECT (Enhanced Capture Timer 16 Bit 8 Channels) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $006C Reserved Write: TIMTST...

  • Page 34

    MC9S12DT256 Device User Guide — V03.07 $0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: ASCIF $0082 ATD0CTL2...

  • Page 35

    MC9S12DT256 Device User Guide — V03.07 $0080 - $009F ATD0 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: Bit7 Bit6 $009B...

  • Page 36

    MC9S12DT256 Device User Guide — V03.07 $00A0 - $00C7 PWM (Pulse Width Modulator 8 Bit 8 Channel) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: Bit 7 Bit 0...

  • Page 37

    MC9S12DT256 Device User Guide — V03.07 $00C8 - $00CF SCI0 (Asynchronous Serial Interface) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $00C8 SBR12 SBR11 SBR10 SBR9 SBR8 SCI0BDH Write:...

  • Page 38

    MC9S12DT256 Device User Guide — V03.07 $00D8 - $00DF SPI0 (Serial Peripheral Interface) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $00DC Reserved Write: Read: $00DD Bit7 Bit0 SPI0DR...

  • Page 39

    MC9S12DT256 Device User Guide — V03.07 $00F0 - $00F7 SPI1 (Serial Peripheral Interface) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $00F0 SPIE SPTIE MSTR CPOL CPHA SSOE LSBFE...

  • Page 40

    MC9S12DT256 Device User Guide — V03.07 $0100 - $010F Flash Control Register (fts256k) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0104 FPROT FPOPEN FPHDIS FPHS1 FPHS0 FPLDIS FPLS1...

  • Page 41

    MC9S12DT256 Device User Guide — V03.07 $0110 - $011B EEPROM Control Register (eets4k) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0119 EADDRLO Bit 7 Bit 0 Write: Read:...

  • Page 42

    MC9S12DT256 Device User Guide — V03.07 $0120 - $013F ATD1 (Analog to Digital Converter 10 Bit 8 Channel) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $012D ATD1DIEN Bit 7...

  • Page 43: Table 1-2 Detailed Mscan Foreground Receive And Transmit Buffer Layout

    MC9S12DT256 Device User Guide — V03.07 $0140 - $017F CAN0 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0143 CAN0BTR1 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10...

  • Page 44

    MC9S12DT256 Device User Guide — V03.07 Table 1-2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read: ID14 ID13 ID12...

  • Page 45

    MC9S12DT256 Device User Guide — V03.07 $0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: RXACT SYNCH $0180 RXFRM CSWAI TIME...

  • Page 46

    MC9S12DT256 Device User Guide — V03.07 $0180 - $01BF CAN1 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0199 CAN1IDAR5 Write: Read: $019A CAN1IDAR6...

  • Page 47

    MC9S12DT256 Device User Guide — V03.07 $0240 - $027F PIM (Port Integration Module PIM_9DP256) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $024D PPSS PPSS7 PPSS6 PPSS5 PPSS4 PPSS3...

  • Page 48

    MC9S12DT256 Device User Guide — V03.07 $0240 - $027F PIM (Port Integration Module PIM_9DP256) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $0266 PIEH PIEH7 PIEH6 PIEH5 PIEH4 PIEH3...

  • Page 49

    MC9S12DT256 Device User Guide — V03.07 $0280 - $02BF CAN4 (Motorola Scalable CAN - MSCAN) Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $028C Reserved Write: Read: $028D Reserved...

  • Page 50: Part Id Assignments

    MC9S12DT256 Device User Guide — V03.07 $02C0 - $03FF Reserved space Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read: $02C0 Reserved - $03FF Write: 1.7 Part ID Assignments The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses $001A and $001B after reset).

  • Page 51: Section 2 Signal Description

    User Guides of the individual IP blocks on the device. 2.1 Device Pinout The MC9S12DT256/MC9S12DJ256/MC9S12DG256 and MC9S12A256 is available in a 112-pin low profile quad flat pack (LQFP) and MC9S12DJ256/MC9S12DG256 and MC9S12A256 is also available in a 80-pin quad flat pack (QFP). Most pins perform two or more functions, as described in the Signal...

  • Page 52: Figure 2-1 Pin Assignments In 112-pin Lqfp

    MC9S12DT256 Device User Guide — V03.07 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 VDDA MOSI1/PWM1/KWP1/PP1 PAD15/AN15/ETRIG1 MISO1/PWM0/KWP0/PP0 PAD07/AN07/ETRIG0 XADDR17/PK3 PAD14/AN14 XADDR16/PK2 PAD06/AN06 XADDR15/PK1 PAD13/AN13 XADDR14/PK0 PAD05/AN05 IOC0/PT0 PAD12/AN12 IOC1/PT1 PAD04/AN04 IOC2/PT2 PAD11/AN11 IOC3/PT3 PAD03/AN03 VDD1 PAD10/AN10 VSS1 MC9S12DT256/MC9S12A256/ PAD02/AN02 IOC4/PT4 MC9S12DJ256/MC9S12DG256 PAD09/AN09 IOC5/PT5 PAD01/AN01 IOC6/PT6...

  • Page 53: Signal Properties Summary

    MC9S12DT256 Device User Guide — V03.07 SS1/PWM3/KWP3/PP3 SCK1/PWM2/KWP2/PP2 VDDA MOSI1/PWM1/KWP1/PP1 PAD07/AN07/ETRIG0 MISO1/PWM0/KWP0/PP0 PAD06/AN06 IOC0/PT0 PAD05/AN05 IOC1/PT1 PAD04/AN04 IOC2/PT2 PAD03/AN03 IOC3/PT3 PAD02/AN02 VDD1 PAD01/AN01 VSS1 PAD00/AN00 MC9S12DJ256 IOC4/PT4 VSS2 80 QFP IOC5/PT5 VDD2 IOC6/PT6 PA7/ADDR15/DATA15 IOC7/PT7 PA6/ADDR14/DATA14 MODC/TAGHI/BKGD PA5/ADDR13/DATA13 ADDR0/DATA0/PB0 PA4/ADDR12/DATA12...

  • Page 54

    MC9S12DT256 Device User Guide — V03.07 Internal Pull Resistor Pin Name Pin Name Pin Name Pin Name Pin Name Power Description Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply Reset CTRL State EXTAL — — — —...

  • Page 55

    MC9S12DT256 Device User Guide — V03.07 Internal Pull Resistor Pin Name Pin Name Pin Name Pin Name Pin Name Power Description Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply Reset CTRL State PERH/ KWH4 MISO2 — —...

  • Page 56: Detailed Signal Descriptions

    MC9S12DT256 Device User Guide — V03.07 Internal Pull Resistor Pin Name Pin Name Pin Name Pin Name Pin Name Power Description Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply Reset CTRL State PERP/ Port P I/O, Interrupt, Channel 4 of...

  • Page 57: Test - Test Pin

    This input only pin enables or disables the on-chip voltage regulator. 2.3.5 XFC — PLL Loop Filter Pin PLL loop filter. Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be avoided.

  • Page 58: Pad7 / An07 / Etrig0 - Port Ad Input Pin Of Atd0

    MC9S12DT256 Device User Guide — V03.07 2.3.9 PAD7 / AN07 / ETRIG0 — Port AD Input Pin of ATD0 PAD7 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD0. It can act as an external trigger input for the ATD0.

  • Page 59: Figure 2-4 Colpitts Oscillator Connections (pe7=1)

    MC9S12DT256 Device User Guide — V03.07 Figure 2-4 Colpitts Oscillator Connections (PE7=1) EXTAL Crystal or ceramic resonator XTAL VSSPLL * Due to the nature of a translated ground Colpitts oscillator a DC voltage bias is applied to the crystal .Please contact the crystal manufacturer for crystal DC...

  • Page 60: Pe6 / Modb / Ipipe1 - Port E I/o Pin 6

    MC9S12DT256 Device User Guide — V03.07 Figure 2-6 External Clock Connections (PE7=0) EXTAL CMOS-COMPATIBLE EXTERNAL OSCILLATOR (VDDPLL-Level) XTAL not connected 2.3.14 PE6 / MODB / IPIPE1 — Port E I/O Pin 6 PE6 is a general purpose input or output pin. It is used as a MCU operating mode select pin during reset.

  • Page 61: Pe2 / R/w - Port E I/o Pin 2

    MC9S12DT256 Device User Guide — V03.07 2.3.18 PE2 / R/W — Port E I/O Pin 2 PE2 is a general purpose input or output pin. In MCU expanded modes of operations, this pin drives the read/write output signal for the external bus. It indicates the direction of data on the external bus.

  • Page 62: Ph2 / Kwh2 / Sck1 - Port H I/o Pin 2

    PJ7 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode. It can be configured as the transmit pin TXCAN for the Motorola Scalable Controller Area Network controller 4 (CAN4) or the serial clock pin SCL of the IIC module.

  • Page 63: Pk[5:0] / Xaddr[19:14] - Port K I/o Pins [5:0]

    PM4 is a general purpose input or output pin. It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controllers 0 or 4 ( CAN0 or CAN4). It can be configured as the master output (during master mode) or slave input pin (during slave mode) MOSI for the Serial Peripheral Interface 0 (SPI0).

  • Page 64: Pm1 / Txcan0 / Txb — Port M I/o Pin 1

    PM1 is a general purpose input or output pin. It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 (CAN0). It can be configured as the transmit pin TXB of the BDLC.

  • Page 65: Pp2 / Kwp2 / Pwm2 / Sck1 — Port P I/o Pin 2

    MC9S12DT256 Device User Guide — V03.07 2.3.47 PP2 / KWP2 / PWM2 / SCK1 — Port P I/O Pin 2 PP2 is a general purpose input or output pin. It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.

  • Page 66: Ps0 / Rxd0 - Port S I/o Pin 0

    PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT). 2.4 Power Supply Pins MC9S12DT256 power and ground pins are described below. NOTE: All VSS pins must be connected together in the application.

  • Page 67: Vdd1, Vdd2, Vss1, Vss2 - Core Power Pins

    MC9S12DT256 Device User Guide — V03.07 2.4.3 VDD1, VDD2, VSS1, VSS2 — Core Power Pins Power is supplied to the MCU through VDD and VSS. Because fast signal transitions place high, short-duration current demands on the power supply, use bypass capacitors with high-frequency characteristics and place them as close to the MCU as possible.

  • Page 68: Vregen - On Chip Voltage Regulator Enable

    MC9S12DT256 Device User Guide — V03.07 Pin Number Nominal Mnemonic Description Voltage 112-pin QFP 2.5 V Provides operating voltage and ground for the Phased-Locked DDPLL Loop. This allows the supply voltage to the PLL to be bypassed independently. Internal power and ground SSPLL generated by internal regulator.

  • Page 69: Section 3 System Clock Description

    MC9S12DT256 Device User Guide — V03.07 Section 3 System Clock Description 3.1 Overview The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules. Figure 3-1 shows the clock connections from the CRG to all modules.

  • Page 70

    MC9S12DT256 Device User Guide — V03.07...

  • Page 71: Section 4 Modes Of Operation

    Section 4 Modes of Operation 4.1 Overview Eight possible modes determine the operating configuration of the MC9S12DT256. Each mode has an associated default memory map and external bus configuration controlled by a further pin. Three low power modes exist for the device.

  • Page 72: Security

    MC9S12DT256 Device User Guide — V03.07 Table 4-2 Clock Selection Based on PE7 PE7 = XCLKS Description Pierce Oscillator/external clock selected Table 4-3 Voltage Regulator VREGEN VREGEN Description Internal Voltage Regulator enabled Internal Voltage Regulator disabled, VDD1,2 and VDDPLL must be supplied externally with 2.5V 4.3 Security...

  • Page 73: Unsecuring The Microcontroller

    MC9S12DT256 Device User Guide — V03.07 4.3.2.2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller. This is accomplished by resetting directly into expanded mode. The internal FLASH and EEPROM will be disabled. BDM operations will be blocked.

  • Page 74: Run

    MC9S12DT256 Device User Guide — V03.07 4.4.4 Run Although this is not a low power mode, unused peripheral modules should not be enabled in order to save power.

  • Page 75: Section 5 Resets And Interrupts

    MC9S12DT256 Device User Guide — V03.07 Section 5 Resets and Interrupts 5.1 Overview Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and interrupts. 5.2 Vectors 5.2.1 Vector Table Table 5-1 lists interrupt sources and vectors in default order of priority.

  • Page 76

    MC9S12DT256 Device User Guide — V03.07 ATD1 I-Bit ATD1CTL2 (ASCIE) $FFD0, $FFD1 Port J I-Bit PTJIF (PTJIE) $FFCE, $FFCF Port H I-Bit PTHIF(PTHIE) $FFCC, $FFCD Modulus Down Counter underflow I-Bit MCCTL(MCZI) $FFCA, $FFCB Pulse Accumulator B Overflow I-Bit PBCTL(PBOVI) $FFC8, $FFC9...

  • Page 77: Effects Of Reset

    MC9S12DT256 Device User Guide — V03.07 5.3 Effects of Reset When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the respective module Block User Guides for register reset states. 5.3.1 I/O pins Refer to the HCS12 Core User Guides for mode dependent pin configuration of port A, B, E and K out of reset.

  • Page 78

    MC9S12DT256 Device User Guide — V03.07...

  • Page 79: Cpu12 Block Description

    MC9S12DT256 Device User Guide — V03.07 Section 6 HCS12 Core Block Description 6.1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU. When the CPU12 Reference Manual refers to cycles this is equivalent to Bus Clock Periods.

  • Page 80: Hcs12 Breakpoint (bkp) Block Description

    Section 9 Analog to Digital Converter (ATD) Block Description There are two Analog to Digital Converters (ATD1 and ATD0) implemented on the MC9S12DT256. Consult the ATD_10B8C Block User Guide for information about each Analog to Digital Converter module.When the ATD_10B8C Block Guide refers to freeze mode this is equivalent to active BDM mode.

  • Page 81

    MC9S12DT256 Device User Guide — V03.07 There are two Serial Communications Interfaces (SCI1 and SCI0) implemented on the MC9S12DT256 device. Consult the SCI Block User Guide for information about each Serial Communications Interface module. Section 12 Serial Peripheral Interface (SPI) Block Description There are three Serial Peripheral Interfaces(SPI2, SPI1 and SPI0) implemented on MC9S12DT256.

  • Page 82

    This module supports single-cycle misaligned word accesses. Section 18 MSCAN Block Description There are three MSCAN modules (CAN4, CAN1 and CAN0) implemented on the MC9S12DT256. Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module. Section 19 Port Integration Module (PIM) Block Description Consult the PIM_9DP256 Block User Guide for information about the Port Integration Module.

  • Page 83

    MC9S12DT256 Device User Guide — V03.07 Component Purpose Type Value VDD1 filter cap ceramic X7R 100 .. 220nF VDD2 filter cap ceramic X7R 100 .. 220nF VDDA filter cap ceramic X7R 100nF VDDR filter cap X7R/tantalum >=100nF VDDPLL filter cap...

  • Page 84: Figure 20-1 Recommended Pcb Layout For 112lqfp Colpitts Oscillator

    MC9S12DT256 Device User Guide — V03.07 Figure 20-1 Recommended PCB Layout for 112LQFP Colpitts Oscillator VSSA VSSX VDDA VDD1 VSS1 VSS2 VDD2 VSSR VDDR VSSPLL VDDPLL...

  • Page 85: Figure 20-2 Recommended Pcb Layout For 80qfp Colpitts Oscillator

    MC9S12DT256 Device User Guide — V03.07 Figure 20-2 Recommended PCB Layout for 80QFP Colpitts Oscillator VSSA VSSX VDDA VDD1 VSS2 VSS1 VDD2 VSSR VDDR VSSPLL VDDPLL...

  • Page 86: Figure 20-3 Recommended Pcb Layout For 112lqfp Pierce Oscillator

    MC9S12DT256 Device User Guide — V03.07 Figure 20-3 Recommended PCB Layout for 112LQFP Pierce Oscillator VSSA VSSX VDDA VDD1 VSS1 VSS2 VDD2 VSSR VSSPLL VDDR VDDPLL...

  • Page 87: Figure 20-4 Recommended Pcb Layout For 80qfp Pierce Oscillator

    MC9S12DT256 Device User Guide — V03.07 Figure 20-4 Recommended PCB Layout for 80QFP Pierce Oscillator VSSA VSSX VDDA VDD1 VSS2 VSS1 VDD2 VSSPLL VSSR VDDR VSSPLL VDDPLL...

  • Page 88

    MC9S12DT256 Device User Guide — V03.07...

  • Page 89: Appendix A Electrical Characteristics

    Those parameters are derived mainly from simulations. A.1.2 Power Supply The MC9S12DT256 utilizes several pins to supply power to the I/O ports, A/D converter, oscillator and PLL as well as the digital core. The VDDA, VSSA pair supplies the A/D converter and the resistor ladder of the internal voltage regulator.

  • Page 90: Pins

    MC9S12DT256 Device User Guide — V03.07 The VDDX, VSSX, VDDR and VSSR pairs supply the I/O pins, VDDR supplies also the internal voltage regulator. VDD1, VSS1, VDD2 and VSS2 are the supply pins for the digital logic, VDDPLL, VSSPLL supply the oscillator and the PLL.

  • Page 91: Current Injection

    MC9S12DT256 Device User Guide — V03.07 A.1.4 Current Injection Power supply must maintain regulation within operating V or V range during instantaneous and operating maximum current conditions. If positive injection current (V > V ) is greater than I , the injection current may flow out of VDD5 and could result in external power supply going out of regulation.

  • Page 92: Esd Protection And Latch-up Immunity

    MC9S12DT256 Device User Guide — V03.07 2. The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute maximum ratings apply when the device is powered from an external source.

  • Page 93: Operating Conditions

    MC9S12DT256 Device User Guide — V03.07 A.1.7 Operating Conditions This chapter describes the operating conditions of the device. Unless otherwise noted those conditions apply to all the following data. NOTE: Please refer to the temperature rating of the device (C, V, M) with regards to the...

  • Page 94

    MC9S12DT256 Device User Guide — V03.07 P D Θ JA • Junction Temperature, [°C ] Ambient Temperature, [°C ] Total Chip Power Dissipation, [W] Θ Package Thermal Resistance, [°C/W] The total power dissipation can be calculated from: P INT Chip Internal Power Dissipation, [W] Two cases with internal voltage regulator enabled and disabled must be considered: 1.

  • Page 95: I/o Characteristics

    MC9S12DT256 Device User Guide — V03.07 Table A-5 Thermal Package Characteristics Num C Rating Symbol Unit θ T Thermal Resistance LQFP112, single sided PCB Thermal Resistance LQFP112, double sided PCB θ with 2 internal planes θ T Thermal Resistance LQFP 80, single sided PCB Thermal Resistance LQFP 80, double sided PCB θ...

  • Page 96: Table A-6 5v I/o Characteristics

    MC9S12DT256 Device User Guide — V03.07 Table A-6 5V I/O Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Unit 0.65*V P Input High Voltage T Input High Voltage VDD5 + 0.3 0.35*V P Input Low Voltage T Input Low Voltage VSS5 - 0.3...

  • Page 97: Supply Currents

    MC9S12DT256 Device User Guide — V03.07 A.1.10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements. A.1.10.1 Measurement Conditions All measurements are without output loads. Unless otherwise noted the currents are measured in single chip mode, internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode.

  • Page 98: Table A-7 Supply Current Characteristics

    MC9S12DT256 Device User Guide — V03.07 given. A very good estimate is to take the single chip currents and add the currents due to the external loads. Table A-7 Supply Current Characteristics Conditions are shown in Table A-4 unless otherwise noted...

  • Page 99: Atd Characteristics

    MC9S12DT256 Device User Guide — V03.07 A.2 ATD Characteristics This section describes the characteristics of the analog to digital converter. A.2.1 ATD Operating Characteristics The Table A-8 shows conditions under which the ATD operates. The following constraints exist to obtain full-scale, full range results: ≤...

  • Page 100: Table A-9 Atd Electrical Characteristics

    MC9S12DT256 Device User Guide — V03.07 specifies results in an error of less than 1/2 LSB (2.5mV) at the maximum leakage current. If device or operating conditions are less than worst case or leakage-induced error is acceptable, larger values of source resistance is allowed.

  • Page 101: Atd Accuracy

    MC9S12DT256 Device User Guide — V03.07 A.2.3 ATD accuracy Table A-10 specifies the ATD conversion performance excluding any errors due to current injection, input capacitance and source resistance. Table A-10 ATD Conversion Performance Conditions are shown in Table A-4 unless otherwise noted = 5.12V.

  • Page 102: Figure A-1 Atd Accuracy Definitions

    MC9S12DT256 Device User Guide — V03.07 10-Bit Absolute Error Boundary $3FF 8-Bit Absolute Error Boundary $3FE $3FD $3FC $3FB $3FA $3F9 $3F8 $3F7 $3F6 $3F5 $3F4 $3F3 Ideal Transfer Curve 10-Bit Transfer Curve 8-Bit Transfer Curve 5055 5060 5065 5070 5075 5080...

  • Page 103: Nvm, Flash And Eeprom

    MC9S12DT256 Device User Guide V03.07 A.3 NVM, Flash and EEPROM NOTE: Unless otherwise noted the abbreviation NVM (Non Volatile Memory) is used for both Flash and EEPROM. A.3.1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator. A minimum oscillator frequency f is required for performing program or erase operations.

  • Page 104: Table A-11 Nvm Timing Characteristics

    MC9S12DT256 Device User Guide V03.07 A.3.1.3 Sector Erase Erasing a 512 byte Flash sector or a 4 byte EEPROM sector takes: ≈ ⋅ 4000 --------------------- NVMOP The setup time can be ignored for this operation. A.3.1.4 Mass Erase Erasing a NVM block takes: ≈...

  • Page 105

    MC9S12DT256 Device User Guide V03.07 3. Maximum Erase and Programming times are achieved under particular combinations of f and bus frequency f NVMOP Refer to formulae in Sections A.3.1.1 - A.3.1.4 for guidance. 4. Burst Programming operations are not applicable to EEPROM 5.

  • Page 106: Nvm Reliability

    MC9S12DT256 Device User Guide V03.07 A.3.2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification, constant process monitors and burn-in to screen early life failures.The program/erase cycle count on the sector is incremented every time a sector or mass erase event is executed...

  • Page 107: Figure A-2 Typical Endurance Vs Temperature

    MC9S12DT256 Device User Guide V03.07 Figure A-2 Typical Endurance vs Temperature Operating Temperature T [°C] ------ Flash ------ EEPROM...

  • Page 108

    MC9S12DT256 Device User Guide V03.07...

  • Page 109: Voltage Regulator

    MC9S12DT256 Device User Guide — V03.07 A.4 Voltage Regulator The on-chip voltage regulator is intended to supply the internal logic and oscillator circuits. No external DC load is allowed. Table A-13 Voltage Regulator Recommended Load Capacitances Rating Symbol Unit Load Capacitance on VDD1, 2...

  • Page 110

    MC9S12DT256 Device User Guide — V03.07...

  • Page 111: Reset, Oscillator And Pll

    MC9S12DT256 Device User Guide — V03.07 A.5 Reset, Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase-Locked-Loop (PLL). A.5.1 Startup Table A-14 summarizes several startup characteristics explained in this section. Detailed description of the startup behavior can be found in the Clock and Reset Generator (CRG) Block Guide.

  • Page 112: Oscillator

    MC9S12DT256 Device User Guide — V03.07 A.5.1.5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes. The controller can be woken up by internal or external interrupts. After t the CPU starts fetching the interrupt vector.

  • Page 113: Phase Locked Loop

    MC9S12DT256 Device User Guide — V03.07 A.5.3 Phase Locked Loop The oscillator provides the reference clock for the PLL. The PLL´s Voltage Controlled Oscillator (VCO) is also the system clock source in self clock mode. A.5.3.1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics.

  • Page 114

    MC9S12DT256 Device User Guide — V03.07 The loop bandwidth f should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10, typical values are 50. ζ = 0.9 ensures a good transient response. 2 ζ f ⋅...

  • Page 115: Figure A-4 Jitter Definitions

    MC9S12DT256 Device User Guide — V03.07 min1 max1 minN maxN Figure A-4 Jitter Definitions The relative deviation of t is at its maximum for one clock period, and decreases towards zero for larger number of clock periods (N). Defining the jitter as: ⎛...

  • Page 116: Table A-16 Pll Characteristics

    MC9S12DT256 Device User Guide — V03.07 This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the effect of the jitter to a large extent. Table A-16 PLL Characteristics Conditions are shown in Table A-4 unless otherwise noted...

  • Page 117: Mscan

    MC9S12DT256 Device User Guide — V03.07 A.6 MSCAN Table A-17 MSCAN Wake-up Pulse Characteristics Conditions are shown in Table A-4 unless otherwise noted Num C Rating Symbol Unit µs P MSCAN Wake-up dominant pulse filtered µs P MSCAN Wake-up dominant pulse pass...

  • Page 118

    MC9S12DT256 Device User Guide — V03.07...

  • Page 119: Spi

    MC9S12DT256 Device User Guide — V03.07 A.7 SPI This section provides electrical parametrics and ratings for the SPI. In Table A-18 the measurement conditions are listed. Table A-18 Measurement Conditions Description Value Unit Drive mode full drive mode — Load capacitance C...

  • Page 120: Figure A-7 Spi Master Timing (cpha=1)

    MC9S12DT256 Device User Guide — V03.07 (OUTPUT) (CPOL = 0) (OUTPUT) (CPOL = 1) (OUTPUT) MISO MSB IN BIT 6 . . . 1 LSB IN (INPUT) MOSI PORT DATA BIT 6 . . . 1 MASTER LSB OUT PORT DATA...

  • Page 121: Slave Mode

    MC9S12DT256 Device User Guide — V03.07 A.7.2 Slave Mode In Figure A-8 the timing diagram for slave mode with transmission format CPHA=0 is depicted. (INPUT) (CPOL = 0) (INPUT) (CPOL = 1) (INPUT) MISO BIT 6 . . . 1...

  • Page 122: Figure A-9 Spi Slave Timing (cpha=1)

    MC9S12DT256 Device User Guide — V03.07 (INPUT) (CPOL = 0) (INPUT) (CPOL = 1) (INPUT) MISO BIT 6 . . . 1 SLAVE MSB OUT SLAVE LSB OUT note (OUTPUT) MOSI MSB IN BIT 6 . . . 1 LSB IN...

  • Page 123: External Bus Timing

    MC9S12DT256 Device User Guide — V03.07 A.8 External Bus Timing A timing diagram of the external multiplexed-bus is illustrated in Figure A-10 with the actual timing values shown on table Table A-21. All major bus signals are included in the diagram. While both a data write and data read cycle are shown, only one or the other would occur on a particular bus cycle.

  • Page 124: Figure A-10 General External Bus Timing

    MC9S12DT256 Device User Guide — V03.07 1, 2 ECLK Addr/Data data data addr (read) PA, PB Addr/Data data data addr (write) PA, PB Non-Multiplexed Addresses PK5:0 LSTRB NOACC IPIPO0 IPIPO1, PE6,5 Figure A-10 General External Bus Timing...

  • Page 125

    MC9S12DT256 Device User Guide — V03.07 Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C = 50pF LOAD Num C Rating Symbol Unit P Frequency of operation (E-clock) 25.0 P Cycle time D Pulse width, E low...

  • Page 126

    MC9S12DT256 Device User Guide — V03.07 Table A-21 Expanded Bus Timing Characteristics Conditions are shown in Table A-4 unless otherwise noted, C = 50pF LOAD Num C Rating Symbol Unit D NOACC hold time D IPIPO[1:0] delay time D IPIPO[1:0] valid time to E rise (PW –t...

  • Page 127: Appendix B Package Information

    MC9S12DT256 Device User Guide — V03.07 Appendix B Package Information B.1 General This section provides the physical dimensions of the MC9S12DT256 packages.

  • Page 128: 112-pin Lqfp Package

    MC9S12DT256 Device User Guide — V03.07 B.2 112-pin LQFP package 0.20 0.20 4X 28 TIPS PIN 1 IDENT VIEW Y 108X X=L, M OR N VIEW Y BASE METAL 0.13 SECTION J1-J1 ° ROTATED 90 COUNTERCLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.

  • Page 129: 80-pin Qfp Package

    MC9S12DT256 Device User Guide — V03.07 B.3 80-pin QFP package -A-,-B-,-D- DETAIL A DETAIL A 0.20 0.05 A-B 0.20 DETAIL C 0.20 SECTION B-B DATUM ° VIEW ROTATED 90 PLANE 0.10 SEATING PLANE NOTES: MILLIMETERS 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

  • Page 130

    MC9S12DT256 Device User Guide — V03.07...

  • Page 131

    MC9S12DT256 Device User Guide — V03.07 User Guide End Sheet...

  • Page 132

    MC9S12DT256 Device User Guide — V03.07 FINAL PAGE OF PAGES...

This manual also for:

Mc9s12a256, Mc9s12dj256, Mc9s12dg256

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