Motorola MPC860 PowerQUICC User Manual page 990

Part VI. Debug and Test
Table 37-20. ICTRL Field Descriptions (Continued)
Bits Name
20 SIW0EN Software trap enable selection of instruction watchpoints 0Ð3.
0 Trap disabled (reset value)
21 SIW1EN
1 Trap enabled
22 SIW2EN
23 SIW3EN
24 DIW0EN Development port trap enable selection of the instruction watchpoints 0Ð3 (read-only bit).
0 Trap disabled (reset value)
25 DIW1EN
1 Trap enabled
26 DIW2EN
27 DIW3EN
28 IFM Ignore Þrst match, only for instruction breakpoints.
0 Do not ignore Þrst match, used for Ògo to xÓ (reset value).
1 Ignore Þrst match (used for ÒcontinueÓ).
29Ð31 ISCT_SE Instruction fetch show cycle/core serialize control. Changing the Instruction show cycle
R programming takes effect only from the second instruction after the mtspr[ICTRL].
000 Core is fully serialized; show cycle is performed for all fetched instructions (reset value =
001 Core is fully serialized; show cycle is performed for all changes in program ßow.
010 Core is fully serialized; show cycle is performed for all indirect changes in program ßow.
011 Core is fully serialized; no show cycles is performed for fetched instructions.
100 Illegal.
101 Core is not serialized (normal mode); show cycle is performed for all changes in the
110 Core is not serialized (normal mode; show cycle is performed for all indirect changes in
111 Core is not serialized (normal mode); no show cycle is performed for fetched
When ISCT_SER = 010 or 110, the STS functionality of OP2/MODCK1/STS must be enabled
by writing 10 or 11 to SIUMCR[DBGC]. The address on the external bus should be sampled
only when STS is asserted.
37.5.1.4 Load/Store Support Comparators Control Register
(LCTRL1)
The load/store support comparators control register (LCTRL1), shown in Figure 37-19, is
used to conÞgure load/store address breakpoint operations.
Bit 0 1 2
Field CTE
Bit 16 17 18
Field CSG CSH
Reset
R/W
SPR
Figure 37-19. Load/Store Support Comparators Control Register (LCTRL1)
37-40
0x00000000).
program ßow. If the fetch of the target of a direct branch is aborted by the core (because
of an exception), the target is not always visible on the external pins. Program trace is
not affected by this phenomenon.
program ßow.
instructions.
3 4 5 6
CTF
19 20 21 22
SUSG SUSH
0000_0000_0000_0000
MPC860 PowerQUICC UserÕs Manual
Description
7 8 9 10
CTG CTH
23 24 25 26
CGBMSK
R/W
156
11 12 13 14 15
CRWE CRWF
27 28 29 30 31
CHBMSK Ñ
MOTOROLA