Table of Contents
Advertisement
J
JTAG reset, 12-3
JTAG signals, 3-15, 13-20
K
KR/RETRY (kill reservation/retry)
signal, 3-5, 13-6, 14-4
L
Load/store
byte-reverse instructions, D-22
floating-point load instructions, D-23
floating-point move instructions, D-24
floating-point store instructions, D-24
integer load instructions, D-21
integer store instructions, D-22
load/store instruction timing, 10-7
load/store multiple instructions, D-22
memory synchronization instructions, D-23
string instructions, D-23
Load/store support AND-OR control (LCTRL2)
register, 37-41
Load/store support comparators control (LCTRL1)
register, 37-40
Load/store unit
BAR updates, 5-6
DAR updates, 5-5
DSISR updates, 5-5
overview, 4-10
Lock/key registers, 11-11
Loop control, 16-42
Low-power stop operation, 11-34
M
M_CASID (MMU current address space ID)
register, 9-23
M_TW (MMU tablewalk special) register, 9-24
M_TWB (MMU tablewalk base) register, 9-23
MAR (memory address register), 16-17
MC68360 quad integrated communications controller
(QUICC),, 1-1
MCR (memory command) register, 16-15
MD_CAM (DMMU CAM entry read) register, 9-28
MD_CTR (DMMU control) register, 9-17
MD_RAM (DMMU RAM entry read 0) register, 9-29
MD_RAM (DMMU RAM entry read 1) register, 9-30
MD_RPN (DMMU real page number) register, 9-22
MD_TWC (DMMU tablewalk control) register, 9-19
MDR (memory data register), 16-16
Memory controller
basic architecture, 16-4
block diagram (single UPM), 16-3
MOTOROLA
INDEX
external master support, 16-51
features summary, 16-1
memory system interface, 16-58
overview, 16-1
page mode extended data-out interface, 16-70
registers, 16-8
memory map
PIP,, 2-9, 2-9
SCC1,, 2-6
SCC4,, 2-8
Memory map reference, 2-1
Memory synchronization
instructions, D-23
Memory system interface, 16-58
MI_CAM (IMMU CAM entry read) register, 9-25
MI_CTR (IMMU control) register, 9-16
MI_RAM (IMMU RAM entry read 1) register, 9-27
MI_RAM0 (IMMU RAM entry read 0) register, 9-26
MI_RPN (IMMU real page number) register, 9-20
MI_TWC (IMMU tablewalk control) register, 9-18
Misaligned accesses, 6-1
MMU (memory management unit)
access protection groups, 9-6
address translation, 9-3
debug registers, 9-25
exceptions, 9-32
features, 9-1
locking TLB entries, 9-33
memory attributes, 9-8
overview, 9-1
programming model, 9-14
protection resolution modes, 9-7
TLB invalidation, 9-34
TLB operation, 9-5
TLB reload, 9-32
translation table structure, 9-9
Modes
BE (big-endian) mode byte ordering, A-2
cascaded, 18-7
clock mode, development port, 37-28
debug mode, development support, 37-32
interlocked handshake mode, 33-15
munged little-endian byte ordering, A-1
PPC-LE (PowerPC little-endian) mode byte
ordering, A-6
pulsed handshake mode, 33-16
restart gate, 18-7
SCC AppleTalk mode, 25-1
SCC asynchronous HDLC mode, 26-1
SCC BISYNC mode, 27-1
SCC Ethernet mode, 28-1
SCC HDLC mode, 24-1
SCC Transparent mode, 29-1
SCC UART mode, 23-1
setting the endian operation mode, A-8
Index
Index--7
Advertisement
Table of Contents
